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FIDO2100 3 - port industrial ethernet dlr switch with ieee1588 data sheet april 10, 2013 1 support@innovasic.com document #: ia211111101 - 0 4 1 - 505 - 883 - 5263 uncontrolled when pr inted or copied 1 - 888 - 824 - 4184 FIDO2100 3 - port industrial ethernet dlr switch with ieee 1588 data sheet
FIDO2100 3 - port industrial ethernet dlr switch with ieee1588 data sheet april 10, 2013 2 support@innovasic.com document #: ia211111101 - 0 4 1 - 505 - 883 - 5263 uncontrolled when pr inted or copied 1 - 888 - 824 - 4184 copyright 2013 by innovasic, inc. published by innovasic, inc. 5635 jefferson st. ne, suite a, albuquerque, new mexico 87109 usa fido ? is a trademark of innovasic, inc.
FIDO2100 3 - port industrial ethernet dlr switch with ieee1588 data sheet april 10, 2013 3 support@innovasic.com document #: ia211111101 - 0 4 1 - 505 - 883 - 5263 uncontrolled when pr inted or copied 1 - 888 - 824 - 4184 table of contents 1 overview ................................ ................................ ................................ ............................... 7 1.1 introduction to device l evel ring protocol ................................ ................................ 8 1.2 introduction to ieee - 1588 ................................ ................................ ........................... 9 2 features ................................ ................................ ................................ ............................... 10 2.1 ieee 802.3 mac details ................................ ................................ .......................... 11 2.1.1 ieee 802.3 full duplex flow control ................................ ..................... 12 2.1.2 half duplex flow control and broadcast/multicast storm prevention ... 13 2.2 ieee 1588 v2 ................................ ................................ ................................ ............ 13 2.2.1 ieee 1588 hardware assist for ordinary clock ................................ ...... 13 2.2.2 ieee 1588 end to end transparent clock ................................ ............... 16 2.3 device level ring (dlr) protocol support ................................ ............................. 17 2.3.1 n etwork loops ................................ ................................ .......................... 18 2.4 cut through forwarding ................................ ................................ ........................... 18 2.5 quality of service ................................ ................................ ................................ ...... 19 2.6 unicast and multicast address filtering ................................ ................................ ... 19 2.7 statistics counters ................................ ................................ ................................ ...... 20 2.8 buffer management ................................ ................................ ................................ ... 20 2.9 supported network topologies ................................ ................................ ................. 21 3 lqfp package ................................ ................................ ................................ ..................... 25 3.1 lqfp package pinout ................................ ................................ ................................ 25 3.2 lqfp pin listing ................................ ................................ ................................ ....... 26 3.3 lqfp package physical dimensions ................................ ................................ ......... 30 4 bga package ................................ ................................ ................................ ...................... 31 4.1 bga package pinout ................................ ................................ ................................ . 31 4.2 bga pin listing ................................ ................................ ................................ ........ 32 4.3 bga package physical dimensions ................................ ................................ .......... 36 5 electrical characteristics ................................ ................................ ................................ ..... 37 5.1 thermal characteristics ................................ ................................ ............................. 38 5.2 pll supply ................................ ................................ ................................ ................ 38 5.3 system clock input ................................ ................................ ................................ .... 38 5.4 reset: power - on - reset, hardware reset and software reset ............................... 39 5.4.1 power - on - reset ................................ ................................ ........................ 39
FIDO2100 3 - port industrial ethernet dlr switch with ieee1588 data sheet april 10, 2013 4 support@innovasic.com document #: ia211111101 - 0 4 1 - 505 - 883 - 5263 uncontrolled when pr inted or copied 1 - 888 - 824 - 4184 5.4.2 hardware reset ................................ ................................ ......................... 39 5.4.3 software reset ................................ ................................ .......................... 39 5.5 test input ................................ ................................ ................................ ................... 39 6 host bus interface ................................ ................................ ................................ ............... 40 6.1 read, host bus inte rface ................................ ................................ ......................... 40 6.2 write, host bus interface ................................ ................................ ....................... 41 7 external mii interface ................................ ................................ ................................ ......... 42 7.1 receive data, external mii interface ................................ ................................ 42 7.2 transmit data, external mii interface ................................ ............................. 43 8 internal mii interface ................................ ................................ ................................ .......... 43 8.1 receive data, internal mii interface ................................ ................................ .. 44 8.2 transmit data, internal mii interface ................................ .............................. 45 9 control and status registers ................................ ................................ ............................... 46 9.1 register map ................................ ................................ ................................ .............. 46 9.2 detailed register explanations ................................ ................................ .................. 51 10 revision history ................................ ................................ ................................ .................. 84 11 for additional information ................................ ................................ ................................ . 84
FIDO2100 3 - port industrial ethernet dlr switch with ieee1588 data sheet april 10, 2013 5 support@innovasic.com document #: ia211111101 - 0 4 1 - 505 - 883 - 5263 uncontrolled when pr inted or copied 1 - 888 - 824 - 4184 list of figures figure 1 FIDO2100 top level block diagram ................................ ................................ ................. 7 figure 2 ieee 1588 hardware assist block diagram ................................ ................................ . 14 figure 3 hierarchical st art topology ................................ ................................ ........................... 21 figure 4 hybrid daisy chain and hierarchical star topology ................................ .................... 22 figure 5 ring topology media redundancy ................................ ................................ ................ 23 figure 6 FIDO2100 lqfp package pinout ................................ ................................ ..................... 25 figure 7 lqfp package physical dimensions ................................ ................................ ............. 30 figure 8 FIDO2100 bga package pinout ................................ ................................ ....................... 31 figure 9 bga package physical dimensions ................................ ................................ ............... 36 figure 10 host interface, read timin g ................................ ................................ ...................... 40 figure 11 host interface, write timing ................................ ................................ .................... 41 figure 12 external mii interface, receive data ................................ ................................ ... 42 figure 13 external mii interface, transmit data ................................ ................................ 43 figure 14 internal mii interface, receive data ................................ ................................ .... 44 figure 15 internal mii interface, transmit data ................................ ................................ . 45
FIDO2100 3 - port industrial ethernet dlr switch with ieee1588 data sheet april 10, 2013 6 support@innovasic.com document #: ia211111101 - 0 4 1 - 505 - 883 - 5263 uncontrolled when pr inted or copied 1 - 888 - 824 - 4184 list of tables table 1 128 - pin lqfp pin list ................................ ................................ ................................ ..... 26 table 2 bga pin list ................................ ................................ ................................ .................... 32 table 3 absolute maximum ratings ................................ ................................ ............................ 37 table 4 esd and latch - up characteristics ................................ ................................ .................. 37 table 5 recommended operating conditions ................................ ................................ .............. 37 table 6 dc characteristics of i/o cells ................................ ................................ ....................... 37 table 7 power consumption (nominal) ................................ ................................ ....................... 38 table 8 thermal resistance characteristics ................................ ................................ ................. 38 table 9 host interface, read timing ................................ ................................ ......................... 40 table 10 host interface, write timing ................................ ................................ ..................... 41 table 11 receive data, external mii interface ................................ ................................ ..... 42 table 12 transmit data, external mii interface ................................ ................................ . 43 table 13 receive data, external mii interface ................................ ................................ ..... 44 table 14 transmit data, external mii interface ................................ ................................ . 45 table 15 register map ................................ ................................ ................................ .................. 46 table 16 document revision history ................................ ................................ ........................... 84
FIDO2100 3 - port industrial ethernet dlr switch with ieee1588 data sheet april 10, 2013 7 support@innovasic.com document #: ia211111101 - 0 4 1 - 505 - 883 - 5263 uncontrolled when pr inted or copied 1 - 888 - 824 - 4184 1 overview the FIDO2100 is part of the innovasic fido ? family of real - time communication products. the FIDO2100 is a managed, 3 - port ethernet switch with support for ieee - 1588 and device level ring (dlr) protocol. the FIDO2100 enhances the capabilities of innovasics line of industrial ethernet product s by providing an infrastructure element with low latency, time synchronization and redundancy for any embedded industrial ethernet solution. the FIDO2100 is an ieee 802.3 standard compl iant, layer 2 switch that is compatible with the ieee 802.1d standard. it has three ports: two are external ports that function as physical ports of a product and one is an internal port that connects to the host cpu. each of the three ports has an ieee 80 2.3 compliant mac and the ports are interconnected with each other through full wire speed, non - blocking switching logic. figure 1 illustrates the top - level blocks of the FIDO2100 architecture. figure 1 FIDO2100 top level block di agram
FIDO2100 3 - port industrial ethernet dlr switch with ieee1588 data sheet april 10, 2013 8 support@innovasic.com document #: ia211111101 - 0 4 1 - 505 - 883 - 5263 uncontrolled when pr inted or copied 1 - 888 - 824 - 4184 the pass - through of traffic is handled swiftly by using cut through forwarding to pass traffic to the other external port. this is accomplished without host cpu intervention, which keeps throughput time host interaction to a minimum and keeps pass t hrough delay to a minimum. the FIDO2100 also has the ability to operate in a dlr configuration, which provides media redundancy amongst its members. host cpu source code is available to provide the ability for the device to be a dlr participant or a dlr su pervisor using the dlr support functions. the FIDO2100 will default to linear topology operation, and when inserted into a ring, will automatically change to dlr operation as a dlr participant. 1.1 introduction to device level ring protocol there are a variety of industrial applications in which ethernet ring topologies are preferable to the star topologies common in enterprise networks. ring networks provide inherent single - point fault tolerance an d reduced connectivity costs. device level ring (dlr) protocol provides a means for detecting, managing and recovering from faults in a ring - based network. dlr supports three classes of devices: 1 ring supervisor C ring supervisors are required to send and process dlr beacon frames at the default beacon interval. 2 ring node, beacon - based C these devices are required to process beacon frames. 3 ring node, announce - based C these devices are not required to process dlr beacon frames, but must be capable of process ing announce frames. a dlr network consists of a ring supervisor and any number of ring nodes. ring nodes incorporate FIDO2100 technology with at least two external ports. the ring supervisor is responsible for generating a beacon at regular intervals. these beacons traverse the ring in each direction. the ring supervisor must be capable of blocking dlr frames to avoid infinite propagation of beacons. faults are detected when beacon traffic is interrupted. there are obviously a number of failure mechani sms and associated recovery strategies. for a detailed explanation of dlr refer to odva documentation - volume ii: ethernet/ip adaptation of cip, chapter 9, section 9 - 5. for definition of the dlr ethernet/ip object, refer to volume ii: ethernet/ip adaptati on of cip, chapter 5, section 5 - 5.
FIDO2100 3 - port industrial ethernet dlr switch with ieee1588 data sheet april 10, 2013 9 support@innovasic.com document #: ia211111101 - 0 4 1 - 505 - 883 - 5263 uncontrolled when pr inted or copied 1 - 888 - 824 - 4184 1.2 introduction to ieee - 1588 the ieee 1588 standard, also known as precision time protocol (ptp), provides a means to synchronize participants in a network to a common time sou rce. each network participant has its own precision time source or ordinary clock. a ptp system consists of some number of ordinary clocks connected to a network. a grandmaster is elected based upon the quality of available time sources and all other par ticipants synchronize directly to it. ptp systems can be expanded through the use of boundary clocks. the boundary clock provides a means to bridge synchronization from one network segment to another. a synchronization master can then be elected for ea ch network segment. the root timing reference remains the grandmaster. ptp is a master - slave protocol. the master and network participants exchange synchronization messages. however, these messages will be delayed as they traverse the network due to the inherent latency of the network infrastructure. to compensate for this latency, ptp includes the concept of a transparent clock. the transparent clock automatically compensates for latency by modifying the timestamps in synchronization messages as they pas s through a given device. the FIDO2100 provides hardware support for both transparent and ordinary clocks.
FIDO2100 3 - port industrial ethernet dlr switch with ieee1588 data sheet april 10, 2013 10 support@innovasic.com document #: ia211111101 - 0 4 1 - 505 - 883 - 5263 uncontrolled when pr inted or copied 1 - 888 - 824 - 4184 2 features ieee 802.3 ? 10/100mbps, half / full duplex ? full duplex flow control ? half duplex back pressure flow control ? broadcast / multicast storm prevention ieee 1588 v2 ? hardware assist for ordinary clock ? end - to - end transparent clock dlr beacons ? capability to processes beacons from 100 ms down to 100 s ? provides auto - generation of beacon frames for supervisor f unctions cut through forwarding ? cut through forwarding minimizes latency for high performance control ? applications such as cip motion ip differentiated services code point (dscp) based quality of service (qos) ? 4 prioritized queues per port incoming filt ering on unicast / multicast traffic ? 256 - entry dynamic unicast mac learning and filtering for 2 external ports ? 128 buffers of 128 bytes for each port statistics counters for 2 external ports supported network topologies: ? hierarchical star with either one of the external ports ? daisy chain / hybrid daisy chain hierarchical star ? dlr media redundancy with hardware support for a single fault tolerant ring protocol ? software for switch & dlr protocol management ? full industrial temperature range - 40 to +85c ? pac kages: ? 128 pin plastic low profile qft ( lqfp ), rohs compliant ? 128 ball grid array ( 10x10mm bga ), rohs compliant
FIDO2100 3 - port industrial ethernet dlr switch with ieee1588 data sheet april 10, 2013 11 support@innovasic.com document #: ia211111101 - 0 4 1 - 505 - 883 - 5263 uncontrolled when pr inted or copied 1 - 888 - 824 - 4184 2.1 ieee 802.3 mac details the FIDO2100 implements an ieee 802.3 standard compliant mac for each of the t hree ports. while beginning a transmission, the mac will transmit 7 bytes of preamble pattern 0x55, followed by one byte of start of frame delimiter 0xd5, followed by the frame data and frame check sequence as per ieee 802.3 specification. while transmitti ng, the mac will enforce an inter - frame gap period of 960 ns at 100mbps speed and 9.6 n s at 10mbps speed as per ieee 802.3 specification. while receiving, the mac can tolerate shrinkage of the inter - frame gap period down to 80 nanoseconds at 100mbps speed and 800 nanoseconds at 10mbps speed. in full duplex mode the mac will ignore carrier sense and collision detect signals from the phy and is ready to transmit after satisfying the inter - frame gap period as per ieee 802.3 specification. in half duplex mode, the mac will wait for the current transmission to complete and the carrier sense signal to be de - asserted. then it will monitor if the carrier sense signal gets asserted in the first 2/3 duration of the inter - frame gap period. if the carrier signal gets as serted within that period, the mac will wait until the carrier sense signal gets de - asserted to restart inter - frame gap period again. if the carrier sense signal gets asserted in the last 1/3 duration of the inter - frame gap it will be ignored as per the ie ee 802.3 specification. the mac is ready for transmission at the end of the inter - frame gap period. if a frame is not available for transmission at the end of the inter - frame gap, the carrier sense signal will be monitored for restarting inter - frame gap pe riod. if the frame transmission has commenced in half duplex mode and the collision signal gets asserted by the phy, transmission of the current frame data will be truncated with a jam pattern of 4 bytes of 0xff. at this point the collision back off and re transmission procedure will start using the truncated binary exponential back off algorithm as per ieee 802.3 specification. at the end of enforcing a jamming pattern, the mac will impose a delay before attempting to retransmit the frame. the delay is an i nteger multiple of a slot time, where one slot time is equal to 512 bits time. the number of slot times to delay before the n th retransmission attempt is chosen as a uniformly distributed random integer r in the range: 0 r < 2 k ; where k = min (n, 10) if sixteen transmission attempts fail with collision for the same frame, the frame will be dropped as per ieee 802.3 specification. the mechanism used to generate the uniformly distributed random number is a free running 10 bit wide linear feedback shift regi ster (lfsr). the lfsr will cycle through all states in 1024 transmit clocks of the port under consideration. depending on the retransmission attempt number n , the most significant k bits of lfsr are used as delay integer r . due to the free running nature o f the lfsr, lock step random number generation in two different devices should not occur. however, a facility is provided whereby the firmware can load a random seed value into the lfsr anytime during operation.
FIDO2100 3 - port industrial ethernet dlr switch with ieee1588 data sheet april 10, 2013 12 support@innovasic.com document #: ia211111101 - 0 4 1 - 505 - 883 - 5263 uncontrolled when pr inted or copied 1 - 888 - 824 - 4184 the mac will drop frames received with error s signaled by the phy device and those with frame check sequence (crc) errors. it will drop frames shorter than 64 bytes as per ieee 802.3 specification. it will drop frames longer than maximum ieee 802.3 tagged frame size of 1522 bytes. the mac will also drop frames with alignment error, i.e. those having a non - integral number of bytes. 2.1.1 ieee 802.3 full duplex flow control the FIDO2100 implements ieee 802.3 compliant full duplex flow control using pause frames. in order to provide optimum performance, a special set of rules are followed for pause frame generation and reception. pause frame reception is enabled on external ports operating in full duplex mode and transmission on the port through which the pause frame was received will be suspended for specified pause duration in the pause frame. pause frame reception is always disabled on the internal port, since the host cpu will always have enough memory for its communications. if speed and duplex modes o f external ports are same and when buffer usage on either one of external ports reaches 95% of buffer capacity, a pause frame will be generated from internal port to host cpu with maximum pause duration. if the buffer situation has not improved at the end of pause duration, additional pause frames will be generated from internal port as needed. when buffer usage on both external ports reaches below 85% of buffer capacity, a pause frame will be generated on internal port with zero pause duration to cancel pa use. if speed and duplex modes of external ports are not same, pause frames will not be generated. for external ports, pause frame generation on a port is enabled only for full duplex mode and when both external ports have same speed and duplex settings. w hen a first external port is operating in full duplex mode and buffer usage on internal port or second external port reaches 95% of buffer capacity a pause frame will be generated on first external port with maximum pause duration. if the buffer situation has not improved at the end of pause duration, additional pause frames will be generated from first external port as needed. when buffer usage on both internal and second external ports reaches below 85% of buffer capacity, a pause frame will be generated on first external port with zero pause duration to cancel pause. if speed and duplex modes of external ports are not same, pause frames will not be generated. obviously, for flow control on FIDO2100 to work properly, the integrated mac on host cpu must sup port flow control as well. most ethernet microprocessors do support this capability and dual port product designer must ensure that the selected host cpu supports flow control.
FIDO2100 3 - port industrial ethernet dlr switch with ieee1588 data sheet april 10, 2013 13 support@innovasic.com document #: ia211111101 - 0 4 1 - 505 - 883 - 5263 uncontrolled when pr inted or copied 1 - 888 - 824 - 4184 2.1.2 half duplex flow control and broadcast/multicast storm prevention the FIDO2100 implements back pressure flow control in half duplex mode. when both external ports are operating in same speed and half duplex mode, and buffer usage on the internal p ort or other external port reaches 95% of buffer capacity, back pressure flow control is activated on the first external port. this continues until the buffer usage on both internal and second external ports reaches below 85% of buffer capacity. when back pressure flow control is activated on a port, the port will continue to transmit frames while it has any. if there is no frame to transmit, the frame will keep the carrier sense signal active by sending the preamble pattern periodically, causing the neighb oring node to back off from transmitting any frames. if speed and duplex modes of external ports are not same, back pressure will not be activated. excessive broadcast frames can overload the cpu of all devices on network, especially io adapters and io blo cks, leading to poor performance. to avoid this, the FIDO2100 implements a broadcast storm prevention mechanism. when received broadcast data within a 100 millisecond period (1 second at 10mbps) reaches about 1% of network bandwidth in a port operating at 100mbps speed, additional broadcast frames received on that port within that period will be dropped. this process is repeated for every 100 millisecond period. in well - engineered networks, broadcast storms do not occur during normal operation and a 1% broa dcast storm limit will never be reached. similarly every port is also monitored for received non - redundancy (non - dlr/brp) multicast frames. when received non - redundancy multicast data within a 10 millisecond period (100 milliseconds at 10mbps) reaches abou t 50% of network bandwidth in a port operating at 100mbps speed, additional nonredundancy multicast frames received on that port within that period will be dropped. this process is repeated for every 10 millisecond period. in well - engineered networks, mult icast storms do not occur during normal operation. 2.2 ieee 1588 v2 2.2.1 i eee 1588 hardware assist for ordinary clock figure 2 below shows a block diagram of the ieee 1588 v2 hardware assist that can be used to implement an ieee 1588 ordinary master or slave clock on an end device. the mii traffic of the internal port between the host cpu and the FIDO2100 is monitored by two independent 1588 frame detection logic blocks, one for the transmit channel and the other for the receive channe l. whenever the timestamp point of a passing transmit/receive frame is reached, a snapshot of the system time counter is saved in a temporary register. when the appropriate 1588 frame type is also detected in the frame, the snapshot is saved from the tempo rary register to the transmit/receive snapshot register. the receive snapshot register contains a sixteen entry fifo, while the transmit snapshot register is a
FIDO2100 3 - port industrial ethernet dlr switch with ieee1588 data sheet april 10, 2013 14 support@innovasic.com document #: ia211111101 - 0 4 1 - 505 - 883 - 5263 uncontrolled when pr inted or copied 1 - 888 - 824 - 4184 single entry register. with the transmit snapshot register, the snapshot will be locked to preve nt overwriting by subsequent frames. the firmware must later clear the lock after it has read the snapshot. with the receive snapshot register, the firmware should read all snapshots while the fifo is not empty. if the fifo becomes full because the firmwar e is slow to read it, additional snapshots will not be saved until the fifo has a free entry. to distinguish saved snapshots, the received frame sequence identifier and source port identity are also locked in the fifo and may be read through appropriate re gisters along with the snapshot. figure 2 ieee 1588 hardware assist block diagram the supported frame mapping for frame detection logic is ptp over udp over ipv4 over ieee 802.3 tagged or untagged frames. the frames detected are based on the master mode bit setting in the time sync control register. in master mode, sync frames are time stamped on transmit and delay_req frames are time stamped on receive. in slave mode, delay_req frames are time stamped on transmit and sync frames are time stamped on receive. in addition, the sub - domain field of frames must match the subdomain configuration register for the snapshot to be saved. the addend register, accumulator and system time counter comprise a frequency compensated clock under fi rmware control. the accumulator adds the addend register to itself on every incoming clock from the oscillator and the overflow signal of the accumulator causes the system time counter to increment. this provides a high precision tunable digital clock whos e frequency of operation can be controlled by firmware through writing suitable values to the addend register.
FIDO2100 3 - port industrial ethernet dlr switch with ieee1588 data sheet april 10, 2013 15 support@innovasic.com document #: ia211111101 - 0 4 1 - 505 - 883 - 5263 uncontrolled when pr inted or copied 1 - 888 - 824 - 4184 while transmit and receive frame detection logic operate independently at 25mhz mii clock rates, the rest of the logic operates at 100mhz clock rate. the addend register and accumulator of frequency compensated clock are 32 - bits wide, while the system time counter is 64 - bits wide. the tunable precision for frequency compensation is better than 1 part per billion (1x10 - 9 ). the procedure for realizi ng various nominal system time frequencies is described below. freqoscillator is the clocking frequency of the time synchronization freqclock is the nominal frequency at which the system time counter is to be incremented. freqdivisionratio = freqoscillator / freqclock (this must always be > 1) freqcompensationvalue = frequency compensation value is the number held in the addend register, which is added to the accumulator once every 1/freqoscillator. the equation for the freqcompensationvalue utilizes the pr ecision of the accumulator and the freqdivisionratio . since the accumulator is 32 bits, the following equation provides the value for the addend register: freqcompensationvalue = 2 32 / freqdivisionratio the hexadecimal representation of the freqcompensati onvalue is the value that is written to the addend register. the following table gives examples of addend values based on a 100 mhz freqoscillator . freq - oscillator freqclock freqdivisionratio freqcompensationvalue 100 mhz 83.33 mhz 1.2 0 xd 5555555 100 mh z 80 mhz 1.25 0 xcccccccd 100 mhz 66.66 mhz 1.5 0 xaaaaaaab the synchronization accuracy between the time master and the slave depend on cumulative accuracy of individual components used in the system. when a time slave is connected directly to the time m aster, a synchronization accuracy of less than 50 ns from master is easily possible. this accuracy is achievable with low cost 50ppm crystal clock oscillators. turbulent air flow over the crystal oscillator should be avoided to prevent rapid temperature ch anges resulting in short term stability errors. some phy devices introduce random delays in transmit and receive paths, which can increase time synchronization errors significantly. it is recommended that the phy devices be investigated for such behavior. any asymmetry in transmit and receive paths should be accounted properly by firmware to avoid accumulation of errors. in a cascaded transparent clock configuration between the time master and the slave, the errors will increase linearly with the number of transparent clocks.
FIDO2100 3 - port industrial ethernet dlr switch with ieee1588 data sheet april 10, 2013 16 support@innovasic.com document #: ia211111101 - 0 4 1 - 505 - 883 - 5263 uncontrolled when pr inted or copied 1 - 888 - 824 - 4184 there are two 64 - bit target time registers and comparators that can be used to generate an interrupt to the host cpu when the system time counter reaches the target time. this feature can be used by firmware to schedule/coordinate contr ol loops/activities. while both target time registers can be used by firmware for any purpose, the second target time register has a special capability to generate a pulse per second signal. the pulse per second signal is required for internal ieee 1588 co mpliance testing, but is not required on shipping products. there are two additional snapshot registers for two external events. these snapshots can be used to synchronize system time with an external clock. for example, the event 1 can be used to synchron ize internal ieee 1588 system time as a slave with a global positioning system (gps) signal as the master. similarly, the event 2 can be used to synchronize internal ieee 1588 system time as a master with an external clock in another module in the system a s the slave. both event snapshots have the same capability/behavior in implementation and they can be used interchangeably. 2.2.2 ieee 1588 end to end transparent clock the FIDO2100 implements an integra ted ieee 1588 v2 end to end transparent clock (e2e tc). this is a single step transparent clock in ieee 1588 terminology. the supported frame mapping is ptp over udp over ipv4 over ieee 802.3 tagged or untagged frames. the e2e tc uses a non - syntonized free running timer as a time base. the free running timer runs at 100mhz, but the timestamp circuit uses both edges of the clock for sampling, and delay computation is suitably adjusted to make it effectively run at 200mhz, with 5 ns resolution. in e2e tc mode , whenever an ieee 1588 v2 sync or delay_req frame is received, a receive timestamp is triggered on ingress at the timestamp point following the start of frame delimiter. the frame is parsed to extract the udp checksum and correction field. when the receiv ed frame doesnt contain any errors and when the frame is transmitted through a port, a transmit timestamp is triggered on egress at the timestamp point. the residence time delay is then computed on the fly from the transmit and receive timestamps. the res idence time delay is then added to the correction field in the frame with the udp checksum and frame crc adjusted on the fly. without transparent clocks, cascaded switches or boundary clocks will accumulate errors at exponential rate making time synchroniz ation unstable. with transparent clocks the accumulation of errors is linear with the number of nodes. the implemented e2e tc has a theoretical worst case error of +/ - 15 ns per node assuming 50ppm source crystal oscillator stability.
FIDO2100 3 - port industrial ethernet dlr switch with ieee1588 data sheet april 10, 2013 17 support@innovasic.com document #: ia211111101 - 0 4 1 - 505 - 883 - 5263 uncontrolled when pr inted or copied 1 - 888 - 824 - 4184 2.3 device level ring (dlr) protocol support the FIDO2100 provides hardware support for a single - fault tolerant ring protocol. the dlr protocol support for non - supervisor mode and support for supervisor mode can be enable d by setting appropriate bits in the redundancy control register. in non - supervisor mode, received non - erroneous dlr beacon frames from the active ring supervisor through either port will be automatically dropped after extracting state information and rest arting the dlr beacon timers. received non - erroneous dlr beacon frames may optionally be configured to be delivered to the host cpu by setting appropriate bits in the redundancy control register. irrespective of this bit setting, beacon messages received f rom a different supervisor than active supervisor are always forwarded to host cpu. the FIDO2100 can be configured to interrupt host cpu when ring beacon frames from active supervisor are received through either port or are not received through either port within ring beacon timeout period. the FIDO2100 can also be configured to interrupt host cpu when a change of state is observed in ring beacon frames from active ring supervisor received through either port. neighbor check and multicast sign on frames rec eived from either external port will be forwarded only to host cpu and those from host cpu will be forwarded only through port number matching source port number field in frame. source identifier and sequence identifier fields of received neighbor check fr ames are captured to identify received port later. unicast sign on frames are treated as any other unicast frame. in supervisor mode, either one of the external ports can be placed in blocked mode by setting appropriate port transmit/receive blocked bits i n redundancy control register. all frame reception and transmission will be blocked by the port in blocked mode with the exception of some special frames. these special frames are described under port transmit/receive blocked bits in redundancy control reg ister. in supervisor mode, ring beacon frames can be automatically generated and transmitted through unblocked ports to reduce the cpu load and their arrival through both ports are monitored. the FIDO2100 can be configured to interrupt the host cpu when dl r beacon frames are received through either port or are not received through either port within dlr beacon timeout period. the FIDO2100 can also be configured to interrupt the host cpu when a change of state is observed in dlr beacon frames are received fr om the active ring supervisor through either port. received non - erroneous dlr beacon frames may optionally be configured to be delivered to host cpu by setting appropriate bits in redundancy control register. irrespective of this bit setting, beacon messag es received from a different supervisor than self is always forwarded to host cpu. in supervisor mode, neighbor check and multicast sign on frames received from either external port will be forwarded only to the host cpu, and those from the host cpu will b e forwarded only through the port number matching the source port number field in the frame. the source identifier and sequence identifier fields of received neighbor check frames and sign on frames are captured to identify the received port later. link/ne ighbor status frames received from either external port will be forwarded
FIDO2100 3 - port industrial ethernet dlr switch with ieee1588 data sheet april 10, 2013 18 support@innovasic.com document #: ia211111101 - 0 4 1 - 505 - 883 - 5263 uncontrolled when pr inted or copied 1 - 888 - 824 - 4184 only to the host cpu. the source identifier and sequence identifier fields of received link/neighbor status frames are captured to identify the received port later. 2.3.1 network loops the FIDO2100 has a built in safety feature to detect network loops. undetected, network loops can cause severe network problems. network loops may be present when the user inadvertently misconnects the network in such a way as to create a loop or when the user intentionally creates a dlr topology, but fails to configure a dlr supervisor. when a frame is received through one of the external ports with the source mac address the same as the mac address of the host cpu, the fido21 00 will drop that frame and will set a port - specific bit in the switch event register indicating that such a frame was received. these bits can be read and cleared by firmware and can be used to flag the network fault situation to the user. alternatively, the FIDO2100 can be configured to interrupt the host cpu when those bits are set. it should be noted that in a properly configured dlr with a dlr supervisor, network loops may be present for short durations when the network is being reconfigured. hence fir mware should not flag the user of this fault condition when operating in proper dlr mode. the firmware can detect the proper dlr mode by the presence of dlr beacons on the network, whereas in non - dlr mode or an improperly configured dlr mode, dlr beacons w ould be absent on network. 2.4 cut through forwarding the FIDO2100 implements cut through forwarding with store and forward on contention at the transmitting port. cots switches and standard switching integrated circui ts typically support only the store and forward approach. with the store and forward approach a frame has to be completely received before being transmitted. hence every frame will encounter a delay equal to the length of the frame and additional internal switching delay. this can become an issue for high performance applications such as cip motion when a long chain of cascaded switches are involved, such as in daisy chain or dlr topology networks. with cut through forwarding, when frame reception begins an d when a sufficient number of bytes of a frame have been buffered, the frame is queued for transmission, subject to the following forwarding rules: 1. if the transmitting port is idle and ready for transmission, it will immediately start frame transmission wh ile the reception is in progress. 2. if the transmitting port is not free immediately, it will start transmitting as soon as the port becomes ready for transmission, while the reception is in progress. 3. if the transmitting port doesnt become available before the entire frame is received, the received frame will be buffered completely for store and forward.
FIDO2100 3 - port industrial ethernet dlr switch with ieee1588 data sheet april 10, 2013 19 support@innovasic.com document #: ia211111101 - 0 4 1 - 505 - 883 - 5263 uncontrolled when pr inted or copied 1 - 888 - 824 - 4184 because of cut through forwarding, non - ip frames from all transmit queues and ip frames from transmit queues 2 and 3 will face a delay of 2.8 s, other non - ieee 1588 frames will face a delay of 4.9 s and ieee 1588 time synchronization frames will face a delay of 7.3 s through the FIDO2100 , when the transmitting port is free of contention. cut through forwarding is disabled for a transmit port when the recei ving port is operating at 10mbps speed and the transmitting port is operating at 100mbps speed. in this case, store and forward is used. 2.5 quality of service in order to support high performance applications such as cip motion, the FIDO2100 enforces quality of service based on ip differentiated services code point (dscp). the FIDO2100 implements four prioritized transmit queues per port. frames received with dscp 59 are queued in the highest priority transmit queue (queue #1). frames received with dscp 55 are queued in the second highest priority transmit queue (queue #2). frames received with dscp 47 and 43 are queued in the third highest priority transmit queue (queue #3). frames received with other dscp values are queue d in the lowest priority transmit queue (queue #4). in addition, dlr protocol frames are queued in the highest priority queue 1. when a port is ready to transmit the next frame, the highest priority frame is chosen from the current set of queued frames for transmission based on strict priority ordering. within a given priority queue frames are transmitted in fifo order. 2.6 unicast and multicast address filtering the FIDO2100 implements 256 entry dynamic unicast mac address learning and filtering mechanism. the unicast mac address learning table is implemented as 4 - way learning/look up table of 64 rows. the 48 - bit source mac address from a frame received on any external port is hashed into 6 - bits by xor o peration of every sixth bit. the hash index identifies the row where one of four locations that is free is used for mac address learning along with associated external port. when none of them is free, the 4th way location is always overwritten. learning is performed on source mac address only from frames with a unicast or multicast destination mac address. automatic aging of learned entries will happen in 4 - 6 minutes, unless learning is refreshed within that period. when a frame with unicast destination ad dress is received through any port, 4 - way simultaneous lookup is performed from entries at hash index location of destination mac address. if the address is found, the frame is forwarded only through associated external port. if the address is not found, t hen it is forwarded through all other external ports. when a frame with unicast destination address is received through one of the external ports and the destination address matches host cpu mac address, then that frame is forwarded only to internal port. the FIDO2100 implements multicast filtering on the internal port for frames received through external ports and no multicast filtering is implemented for the external ports. the multicast filter consists of a 2048 bin hash table. the received multicast des tination address is passed through a 32 - bit ethernet
FIDO2100 3 - port industrial ethernet dlr switch with ieee1588 data sheet april 10, 2013 20 support@innovasic.com document #: ia211111101 - 0 4 1 - 505 - 883 - 5263 uncontrolled when pr inted or copied 1 - 888 - 824 - 4184 crc generator and the least significant 11 bits of the resulting crc is used to index into the 2048 bin hash table. when the indexed bin in the hash table is set, the frame will be forwarded to the inter nal port and the other external port. if not set, the frame will be forwarded only to the other external port. by default, all 2048 bins of the multicast hash table are set to zero after power up or chip reset, and no multicast frames will be forwarded to the internal port. since most devices such as i/o devices dont need to receive multicast frames, they dont need to change this default behavior. note that the multicast filter table need not be set for receiving multicast ring frames. 2.7 statistics counters the FIDO2100 implements statistics counters for the external ports. these counters can be used by firmware for the media and interface counters of the ethernet/ip ethernet link object (class code: 0xf6). most of thes e counters are 16 bits wide and to avoid roll over issues, firmware must read these registers at least once every 200 milliseconds or on demand, to calculate an increase in counter values. the firmware can then add the increase to firmware maintained 32 bi t counters. counters are implemented for valid frames received with the group bit set in the destination address, valid frames received with a unicast destination address, total byte count of valid frames received, frames received with length greater than 1522 bytes, frames received with alignment error, frames received with a frame check sequence (crc) error and frames received with other errors, including short runt frames less than 64 bytes in length. counters are also implemented for valid frames transm itted with the group bit set in the destination address, valid frames transmitted with a unicast destination address, total byte count of valid frames transmitted, frames transmitted after exactly one collision, frames transmitted after multiple collisions , frames dropped due to excessive collisions and frames truncated with error during transmission. 2.8 buffer management the FIDO2100 implements an efficient packet buffering scheme using on board dual port sram memory. the buffers are 128 bytes in size to minimize memory wastage. frames longer than 128 bytes are automatically fragmented to be stored in multiple buffers and reassembled during transmission. actual buffer usage depends on a number of factors such as network loa d, number of frames waiting to be transmitted at each node at the same time, the number of back to back frames arriving at the destination node through both external ports at the same time, etc. for some devices such as motion drives and i/o, buffer usage on any port may never exceed 10% of buffer capacity. for other devices such as network bridges, buffer usage on any port may be typically less than 50% of buffer capacity during normal operation. irrespective of the type of end device, when buffer usage re aches 95% of buffer capacity on any port under heavily loaded network conditions, flow control will intervene to reduce buffer usage and will ensure frames are not being dropped.
FIDO2100 3 - port industrial ethernet dlr switch with ieee1588 data sheet april 10, 2013 21 support@innovasic.com document #: ia211111101 - 0 4 1 - 505 - 883 - 5263 uncontrolled when pr inted or copied 1 - 888 - 824 - 4184 2.9 supported network topologies dual port products designed with this toolkit can be used in a wide variety of network configurations. this single hardware design will support various network topologies. irrespective of the network configuration used, a dual port end device will always h ave a single ip address and a single mac address. this simplifies both configuration requirements and firmware changes required. figure 3 shows hierarchical star topology with commercial off the shelf (cots) switches. either port of a dual port end device may be used to connect to cots switch to realize hierarchical star network topology. figure 3 hierarchical start topology figure 4 shows a hybrid daisy chain and hierarchical star topology. single port end devices can be connected to a daisy chain at one of the ends of the chain, or through a standalone three port device that provides the daisy chain capability in the middle of chain. figure 3 also shows a cots switch in the middle of a daisy chain.
FIDO2100 3 - port industrial ethernet dlr switch with ieee1588 data sheet april 10, 2013 22 support@innovasic.com document #: ia211111101 - 0 4 1 - 505 - 883 - 5263 uncontrolled when pr inted or copied 1 - 888 - 824 - 4184 figure 4 hybrid daisy chain and hierarchical star topology it should be noted that a slower speed or half duplex link on main daisy chain will become a bottle neck, causing the entire network to operate at reduced capacity. similarly, a single po rt device can be connected to either end of main daisy chain network, only if it operates at same/better speed and duplex mode as rest of the network. the recommended method for connecting slower speed/duplex devices is through a three port tap device to a void performance issues. figure 5 shows a ring topology media redundancy that can tolerate single faults. one or more dlr supervisor(s) control the operation of ring. when multiple dlr supervisors are configured, one of them will be automatically chosen as active supervisor. others will be in passive mode, until the active dlr supervisor fails or is removed from ring.
FIDO2100 3 - port industrial ethernet dlr switch with ieee1588 data sheet april 10, 2013 23 support@innovasic.com document #: ia211111101 - 0 4 1 - 505 - 883 - 5263 uncontrolled when pr inted or copied 1 - 888 - 824 - 4184 figure 5 ring topology media redundancy for io applications, a cots switch in the ring must support ieee 802.3 tag based and ip dscp based qos with at least two prioritized queues, preferably four prioritized queues. the highest priority queue must be dedicated for ring protocol messages for predictable performance. for ieee 1588 applications such as cip motion, co ts switches directly on ring must support ieee 1588 end - to - end transparent clock (or boundary clock) and ieee 802.3 tag based and ip dscp based qos with four prioritized queues. the highest priority queue may be shared between ieee 1588 and ring protocol m essages. if not, cots switches can be connected through three port t ap device as shown in figure 4.
FIDO2100 3 - port industrial ethernet dlr switch with ieee1588 data sheet april 10, 2013 24 support@innovasic.com document #: ia211111101 - 0 4 1 - 505 - 883 - 5263 uncontrolled when pr inted or copied 1 - 888 - 824 - 4184 the cots switch must be configured so that ring protocol messages are not forwarded to devices connected to it. igmp snooping and multicast filtering must be disabled on 2 ports of the cots switch directly connected to ring to facilitate rapid network reconfiguration. since unicast filtering cannot be disabled in a cots switch, it may take couple of cip connection rpis for some data packets to be delivered correctly on some nodes after a network reconfiguration. ring timing parameters such as beacon period and timeout must account for the presence of a cots switch directly in ring. typical network recovery time for a ring containing 50 nodes will be less th an 1 millisecond for most types of faults on a loaded network with mostly ethernet/ip frames. further details of ring topology and protocol are described in, device level ring protocol ; see cip networks library, volume 2, chapter 9, edition 1.7 or later (see www.odva.org for details). it is possible to create complex ring topologies. some examples are: a backbone ring connecting multiple star topologies; a backbone star connecting multiple ring topologies; a backbone r ing connecting multiple ring topologies; and other combinations. most dual/three port devices operate as simple ring nodes and require no special configuration. by default they will power up in daisy chain mode and transparently switch to ring mode upon re ceiving beacon frames from ring supervisor.
FIDO2100 3 - port industrial ethernet dlr switch with ieee1588 data sheet april 10, 2013 25 support@innovasic.com document #: ia211111101 - 0 4 1 - 505 - 883 - 5263 uncontrolled when pr inted or copied 1 - 888 - 824 - 4184 3 lqfp package 3.1 lqfp package pinout the pinout for the FIDO2100 industrial ethernet switch lqfp package is as shown in figure 6 . the corresponding pinout is provided in table 1 . fig ure 6 FIDO2100 lqfp packag e pinout
FIDO2100 3 - port industrial ethernet dlr switch with ieee1588 data sheet april 10, 2013 26 support@innovasic.com document #: ia211111101 - 0 4 1 - 505 - 883 - 5263 uncontrolled when pr inted or copied 1 - 888 - 824 - 4184 3.2 lqfp pin listing table 1 128 - pin lqfp pin list pin signal name type lqfp pin descripti ons 1 sw_event_irq_n output switch event irq, must be connected to a high priority irq pin on cpu 2 ts_event_irq_n output time sync event irq. optional for non - 1588 devices. 3 pps_sig output pulse per second signal for 1588 compliance 4 event_1_sig inp ut external event 1 snapshot trigger from cpu/others 5 event_2_sig input external event 2 snapshot trigger from cpu/others 6 p1_txc input port 1 mii, transmit clock from phy 7 vcck power 1.8 v digital core supply voltage 8 gndk ground digital core grou nd 9 gndio ground i/o ground 10 vcc3io power 3.3 v i/o supply voltage 11 p1_txen output port 1 mii, transmit enable to phy 12 p1_txer output port 1 mii, transmit error to phy 13 p1_txd[0] output port 1 mii, transmit data bit 0 to phy 14 p1_txd[1] out put port 1 mii, transmit data bit 1 to phy 15 p1_txd[2] output port 1 mii, transmit data bit 2 to phy 16 p1_txd[3] output port 1 mii, transmit data bit 3 to phy 17 p1_rxc input port 1 mii, receive clock from phy 18 p1_rxdv input port 1 mii, receive da ta valid from phy 19 p1_rxer input port 1 mii, receive data error from phy 20 p1_rxd[0] input port 1 mii, receive data bit 0 from phy 21 p1_rxd[1] input port 1 mii, receive data bit 1 from phy 22 p1_rxd[2] input port 1 mii, receive data bit 2 from phy 23 vcc3io power 3.3 v i/o supply voltage 24 gndio ground i/o ground 25 gndk ground digital core ground 26 vcck power 1.8 v digital core supply voltage 27 p1_rxd[3] input port 1 mii, receive data bit 3 from phy 28 p1_col input port 1 mii, collision fr om phy 29 p1_crs input port 1 mii, carrier sense from phy 30 p1_lnk_stts input port 1 mii, link status from phy (1:link pass, 0:link fail) 31 p1_led_grn output port 1 mii,, green led 32 p1_led_ylw output port 1 mii,, yellow led 33 p2_txc input port 2 mii, transmit clock from phy 34 p2_txen output port 2 mii, transmit enable to phy 35 p2_txer output port 2 mii, transmit error to phy
FIDO2100 3 - port industrial ethernet dlr switch with ieee1588 data sheet april 10, 2013 27 support@innovasic.com document #: ia211111101 - 0 4 1 - 505 - 883 - 5263 uncontrolled when pr inted or copied 1 - 888 - 824 - 4184 pin signal name type lqfp pin descripti ons 36 p2_txd[0] output port 2 mii, transmit data bit 0 to phy 37 p2_txd[1] output port 2 mii, transmit data bit 1 to phy 38 p2_txd[2] output port 2 mii, transmit data bit 2 to phy 39 vcck power 1.8 v digital core supply voltage 40 gndk ground digital core ground 41 gndio ground i/o ground 42 vcc3io power 3.3 v i/o supply voltage 43 p2_txd[3] output port 2 mii, transmit data bit 3 to phy 44 p2_rxc input port 2 mii, receive clock from phy 45 p2_rxdv input port 2 mii, receive data valid from phy 46 p2_rxer input port 2 mii, receive data error from phy 47 gndo ground i/o ground 48 vdd3o power 3.3 v i/o supply voltage 49 p2_rxd[0] input port 2 mii, receive data bit 0 from phy 50 p2_rxd[1] input port 2 mii, receive data bit 1 from phy 51 p2_rxd[2] input port 2 mii, receive data bit 2 from phy 52 p2_rxd[3] input port 2 mii, receive data, bit 3 from phy 53 p2_col inpu t port 2 mii, collision from phy 54 p2_crs input port 2 mii, carrier sense from phy 55 vcc3io power 3.3 v i/o supply voltage 56 gndio ground i/o ground 57 gndk ground digital core ground 58 vcck power 1.8 v digital core supply voltage 59 p2_lnk_stts input port 2 mii, link status from phy (1:link pass, 0:link fail) 60 p2_led_grn output port 2 mii,, green led 61 p2_led_ylw output port 2 mii,, yellow led 62 reset_n input chip reset, active low (internal pull - up) 63 sys_clk input 25 mhz system clock 64 test input test, active high (internal pull - down) 65 cpu_txen input cpu mii, transmit enable from cpu 66 vcc18a_pll power 1.8 v analog supply voltage 67 gnda_pll ground analog ground 68 cpu_txer input cpu mii, transmit error from cpu 69 cpu_txc out put cpu mii, 25 mhz transmit clock to cpu 70 cpu_txd[0] input cpu mii, transmit data bit 0 from cpu 71 vcck power 1.8 v digital core supply voltage 72 gndk ground digital core ground 73 gndio ground i/o ground 74 vcc3io power 3.3 v i/o supply voltage 75 cpu_txd[1] input cpu mii, transmit data bit 1 from cpu
FIDO2100 3 - port industrial ethernet dlr switch with ieee1588 data sheet april 10, 2013 28 support@innovasic.com document #: ia211111101 - 0 4 1 - 505 - 883 - 5263 uncontrolled when pr inted or copied 1 - 888 - 824 - 4184 pin signal name type lqfp pin descripti ons 76 cpu_txd[2] input cpu mii, transmit data bit 2 from cpu 77 cpu_txd[3] input cpu mii, transmit data bit 3 from cpu 78 cpu_rxc output cpu mii, 25 mhz receive clock to cpu 79 cpu_rxdv output cpu _mii, receive data valid to cpu 80 vcc3o power 3.3 v i/o supply voltage 81 cpu_rxer output cpu mii, receive error 82 cpu_crs output cpu mii, 83 cpu_col output cpu mii, collision 84 cpu_rxd[0] output cpu mii, receive data bit 0 to cpu 85 cpu_rxd[1] o utput cpu mii, receive data bit 1 to cpu 86 cpu_rxd[2] output cpu mii, receive data bit 2 to cpu 87 vcc3io power 3.3 v i/o supply voltage 88 gndio ground i/o ground 89 gndk ground digital core ground 90 vcck power 1.8 v digital core supply voltage 91 cpu_rxd[3] output cpu mii, receive data bit 3 to cpu 92 cpu_adrs[1] input cpu host interface, address bit 1 93 cpu_adrs[2] input cpu host interface, address bit 2 94 cpu_adrs[3] input cpu host interface, address bit 3 95 cpu_adrs[4] input cpu host int erface, address bit 4 96 cpu_adrs[5] input cpu host interface, address bit 5 97 cpu_adrs[6] input cpu host interface, address bit 6 98 cpu_adrs[7] input cpu host interface, address bit 7 99 cpu_adrs[8] input cpu host interface, address bit 8 100 cpu_d ata[0] bidir cpu host interface, data bit 0 101 cpu_data[1] bidir cpu host interface, data bit 1 102 cpu_data[2] bidir cpu host interface, data bit 2 103 vcck power 1.8 v digital core supply voltage 104 gndk ground digital core ground 105 gndio gro und i/o ground 106 vcc3io power 3.3 v i/o supply voltage 107 cpu_data[3] bidir cpu host interface, data bit 3 108 cpu_data[4] bidir cpu host interface, data bit 4 109 cpu_data[5] bidir cpu host interface, data bit 5 110 cpu_data[6] bidir cpu host interface, data bit 6 111 cpu_data[7] bidir cpu host interface, data bit 7 112 gndo ground i/o ground 113 vcc3o power 3.3 v i/o supply voltage 114 cpu_data[8] bidir cpu host interface, data bit 8 115 cpu_data[9] bidir cpu host interface, data bit 0
FIDO2100 3 - port industrial ethernet dlr switch with ieee1588 data sheet april 10, 2013 29 support@innovasic.com document #: ia211111101 - 0 4 1 - 505 - 883 - 5263 uncontrolled when pr inted or copied 1 - 888 - 824 - 4184 pin signal name type lqfp pin descripti ons 116 cpu_data[10] bidir cpu host interface, data bit 10 117 cpu_data[11] bidir cpu host interface, data bit 11 118 cpu_data[12] bidir cpu host interface, data bit 12 119 vcc3io power 3.3 v i/o supply voltage 120 gndio ground i/o ground 121 gndk gr ound digital core ground 122 vcck power 1.8 v digital core supply voltage 123 cpu_data[13] bidir cpu host interface, data bit 13 124 cpu_data[14] bidir cpu host interface, data bit 14 125 cpu_data[15] bidir cpu host interface, data bit 15 126 cpu_c s_n input cpu host interface, chip select, active low (internal pull - up) 127 cpu_rd_n input cpu host interface, read enable, active low (internal pull - up) 128 cpu_wr_n input cpu host interface, write enable, active low (internal pull - up)
FIDO2100 3 - port industrial ethernet dlr switch with ieee1588 data sheet april 10, 2013 30 support@innovasic.com document #: ia211111101 - 0 4 1 - 505 - 883 - 5263 uncontrolled when pr inted or copied 1 - 888 - 824 - 4184 3.3 lqfp package physical dimensions figure 7 lqfp package physical dimensions
fido ? 2100 3 - port industrial ethernet dlr switch with ieee1588 data sheet april 10, 2013 31 support@innovasic.com document #: ia211111101 - 0 4 1 - 505 - 883 - 5263 uncontrolled when pr inted or copied 1 - 888 - 824 - 4184 4 bga package 4.1 bga package pinout the pinout for the FIDO2100 industrial ethernet switch bga package is as shown in figure 8. the corresponding pinout is provided in table 2 . m p1_lnk_stts p2_txc p2_txd[0] p2_txd[2] p2_rxc p2_rxdv p2_rxd[0] p2_rxd[2] p2_col p2_lnk_stts p2_led_grn reset_n l p1_col p1_led_grn p2_txen p2_txd[1] p2_txd[3] p2_rxer p2_rxd[1] p2_rxd[3] p2_crs p2_led_ylw sys_clk cpu_txen k p1_rxd[2] p1_crs p1_led_ylw p2_txer vcck vcc3io vcc3io vcc3io vcck test cpu _txer cpu_txd[0] j p1_rxd[1] p1_rxd[3] vcck vcck gndio vcc18a_pll cpu_txc cpu_txd[2] h p1_rxer p1_rxd[0] vcc3io gndio gndk gndk gndio gnda_pll cpu_txd[1] cpu_txd[3] g p1_rxc p1_rxdv vcc3io gndio gndk gndk gndio vcck cpu_rxc cpu_rxdv f p1_txd[3] p1_txd[2] vcc3io gndio gndk gndk gndio vcc3io cpu_rxer cpu_crs e p1_txd[1] p1_txd[0] vcck gndio gndk gndk gndio vcc3io cpu_rxd[0] cpu_col d p1_txer p1_txc vcck gndio vcck vcc3io cpu_rxd[2] cpu_rxd[1] c p1_txen event_1_sig sw_event_irq_n cpu_cs_ n vcc3io cpu_data[9] cpu_data[5] vcc3io cpu_adrs[8] cpu_adrs[5] cpu_adrs[2] cpu_rxd[3] b event_2_sig ts_event_irq_n cpu_rd_n cpu_data[14] cpu_data[12] cpu_data[10] cpu_data[6] cpu_data[3] cpu_data[1] cpu_adrs[7] cpu_adrs[4] cpu_adrs[1] a pps_sig cpu_wr_n cpu_data[15] cpu_data[13] cpu_data[11] cpu_data[8] cpu_data[7] cpu_data[4] cpu_data[2] cpu_data[0] cpu_adrs[6] cpu_adrs[3] 1 2 3 4 5 6 7 8 9 10 11 12 figure 8 FIDO2100 bga p ackage pinout
FIDO2100 3 - port industrial ethernet dlr switch with ieee1588 data sheet april 10, 2013 32 support@innovasic.com document #: ia211111101 - 0 4 1 - 505 - 883 - 5263 uncontrolled when pr inted or copied 1 - 888 - 824 - 4184 4.2 bga pin listing table 2 bga pin list pin signal name type bga pin descriptions c3 sw_event_irq_n output switch event irq, must be connected to a high priority irq pin on cpu b2 ts_event_irq_n output time sync event irq. optional for non - 1588 devices. a1 pps_sig output pulse per second signal for 1588 compliance c2 event_1_sig input external event 1 snapshot trigger from cpu/others b1 event_2_sig input external event 2 snapshot trigger from cpu/others d2 p1_txc input port 1 mii, transmit clock from phy e3 vcck power 1.8 v digital core supply voltage e6 gndk ground digital core ground f5 gndio ground i/o ground f3 vcc3io power 3.3 v i/o supply voltage c1 p1_txen output port 1 mii, transmit enable to phy d1 p1_txer output port 1 mii, transmit error to phy e2 p1_txd[0] output port 1 mii, transmit data bit 0 to phy e1 p1_txd[1] output port 1 mii, transmit data bit 1 to phy f2 p1_txd[2] output port 1 mii, transmit data bit 2 to phy f1 p1_txd[3] output port 1 mii, transmit data bit 3 to phy g1 p1_rxc input port 1 mii, receive clock from phy g2 p1_rxdv input port 1 mii, receive data valid from phy h1 p1_rxer input port 1 mii, receive data error from phy h2 p1_rxd[0] input port 1 mii, receive data bit 0 from phy j1 p1_rxd[1] input port 1 mii, receive data bit 1 from phy k1 p1_rxd[2] input port 1 mii, receive data bit 2 from phy g3 vcc3io power 3.3 v i/o supply voltage g5 g ndio ground i/o ground f6 gndk ground digital core ground j3 vcck power 1.8 v digital core supply voltage j2 p1_rxd[3] input port 1 mii, receive data bit 3 from phy l1 p1_col input port 1 mii, collision from phy k2 p1_crs input port 1 mii, carrier sen se from phy m1 p1_lnk_stts input port 1 mii, link status from phy (1:link pass, 0:link fail) l2 p1_led_grn output port 1 mii,, green led k3 p1_led_ylw output port 1 mii,, yellow led m2 p2_txc input port 2 mii, transmit clock from phy
FIDO2100 3 - port industrial ethernet dlr switch with ieee1588 data sheet april 10, 2013 33 support@innovasic.com document #: ia211111101 - 0 4 1 - 505 - 883 - 5263 uncontrolled when pr inted or copied 1 - 888 - 824 - 4184 pin signal name type bga pin descriptions l3 p2_txen output port 2 mii, transmit enable to phy k4 p2_txer output port 2 mii, transmit error to phy m3 p2_txd[0] output port 2 mii, transmit data bit 0 to phy l4 p2_txd[1] output port 2 mii, transmit data bit 1 to phy m4 p2_txd[2] output port 2 mii, transmit data bit 2 to phy j4 vcck power 1.8 v digital core supply voltage g6 gndk ground digital core ground h5 gndio ground i/o ground h3 vcc3io power 3.3 v i/o supply voltage l5 p2_txd[3] output port 2 mii, transmit data bit 3 to phy m5 p2_rxc input port 2 mii, receive clock from phy m6 p2_rxdv input port 2 mii, receive data valid from phy l6 p2_rxer input port 2 mii, receive data error from phy j9 gndio ground i/o ground k6 vcc3io power 3.3 v i/o supply voltage m7 p2_rxd[0] input port 2 mii, receive data bit 0 from phy l7 p2_rxd[1] input port 2 mii, receive data bit 1 from phy m8 p2_rxd[2] input port 2 mii, receive data bit 2 from phy l8 p2_rxd[3] input port 2 mii, receive data, bit 3 from phy m9 p2_col input port 2 mii, collision from phy l9 p2_crs i nput port 2 mii, carrier sense from phy k7 vcc3io power 3.3 v i/o supply voltage h8 gndio ground i/o ground h6 gndk ground digital core ground k5 vcck power 1.8 v digital core supply voltage m10 p2_lnk_stts input port 2 mii, link status from phy (1:li nk pass, 0:link fail) m11 p2_led_grn output port 2 mii,, green led l10 p2_led_ylw output port 2 mii,, yellow led m12 reset_n input chip reset, active low (internal pull - up) l11 sys_clk input 25 mhz system clock k10 test input test, active high (intern al pull - down) l12 cpu_txen input cpu mii, transmit enable from cpu j10 vcc18a_pll power 1.8 v analog supply voltage h10 gnda_pll ground analog ground k11 cpu_txer input cpu mii, transmit error from cpu j11 cpu_txc output cpu mii, 25 mhz transmit clock to cpu k12 cpu_txd[0] input cpu mii, transmit data bit 0 from cpu k9 vcck power 1.8 v digital core supply voltage
FIDO2100 3 - port industrial ethernet dlr switch with ieee1588 data sheet april 10, 2013 34 support@innovasic.com document #: ia211111101 - 0 4 1 - 505 - 883 - 5263 uncontrolled when pr inted or copied 1 - 888 - 824 - 4184 pin signal name type bga pin descriptions h7 gndk ground digital core ground g8 gndio ground i/o ground k8 vcc3io power 3.3 v i/o supply voltage h11 cpu_txd[1] input cpu mii, tr ansmit data bit 1 from cpu j12 cpu_txd[2] input cpu mii, transmit data bit 2 from cpu h12 cpu_txd[3] input cpu mii, transmit data bit 3 from cpu g11 cpu_rxc output cpu mii, 25 mhz receive clock to cpu g12 cpu_rxdv output cpu_mii, receive data valid to cpu f10 vcc3io power 3.3 v i/o supply voltage f11 cpu_rxer output cpu mii, receive error f12 cpu_crs output cpu mii, e12 cpu_col output cpu mii, collision e11 cpu_rxd[0] output cpu mii, receive data bit 0 to cpu d12 cpu_rxd[1] output cpu mii, receiv e data bit 1 to cpu d11 cpu_rxd[2] output cpu mii, receive data bit 2 to cpu e10 vcc3io power 3.3 v i/o supply voltage f8 gndio ground i/o ground g7 gndk ground digital core ground g10 vcck power 1.8 v digital core supply voltage c12 cpu_rxd[3] outpu t cpu mii, receive data bit 3 to cpu b12 cpu_adrs[1] input cpu host interface, address bit 1 c11 cpu_adrs[2] input cpu host interface, address bit 2 a12 cpu_adrs[3] input cpu host interface, address bit 3 b11 cpu_adrs[4] input cpu host interface, addre ss bit 4 c10 cpu_adrs[5] input cpu host interface, address bit 5 a11 cpu_adrs[6] input cpu host interface, address bit 6 b10 cpu_adrs[7] input cpu host interface, address bit 7 c9 cpu_adrs[8] input cpu host interface, address bit 8 a10 cpu_data[0] bi dir cpu host interface, data bit 0 b9 cpu_data[1] bidir cpu host interface, data bit 1 a9 cpu_data[2] bidir cpu host interface, data bit 2 d9 vcck power 1.8 v digital core supply voltage f7 gndk ground digital core ground e8 gndio ground i/o ground d10 vcc3io power 3.3 v i/o supply voltage b8 cpu_data[3] bidir cpu host interface, data bit 3 a8 cpu_data[4] bidir cpu host interface, data bit 4 c7 cpu_data[5] bidir cpu host interface, data bit 5
FIDO2100 3 - port industrial ethernet dlr switch with ieee1588 data sheet april 10, 2013 35 support@innovasic.com document #: ia211111101 - 0 4 1 - 505 - 883 - 5263 uncontrolled when pr inted or copied 1 - 888 - 824 - 4184 pin signal name type bga pin descriptions b7 cpu_data[6] bidir cpu host interface, data bit 6 a7 cpu_data[7] bidir cpu host interface, data bit 7 e5 gndio ground i/o ground c8 vcc3io power 3.3 v i/o supply voltage a6 cpu_data[8] bidir cpu host interface, data bit 8 c6 cpu_data[9] bidir cpu host interface, data bit 0 b6 cpu_data[10] bid ir cpu host interface, data bit 10 a5 cpu_data[11] bidir cpu host interface, data bit 11 b5 cpu_data[12] bidir cpu host interface, data bit 12 c5 vcc3io power 3.3 v i/o supply voltage d4 gndio ground i/o ground e7 gndk ground digital core ground d3 vcck power 1.8 v digital core supply voltage a4 cpu_data[13] bidir cpu host interface, data bit 13 b4 cpu_data[14] bidir cpu host interface, data bit 14 a3 cpu_data[15] bidir cpu host interface, data bit 15 c4 cpu_cs_n input cpu host interface, chi p select, active low (internal pull - up) b3 cpu_rd_n input cpu host interface, read enable, active low (internal pull - up) a2 cpu_wr_n input cpu host interface, write enable, active low (internal pull - up)
FIDO2100 3 - port industrial ethernet dlr switch with ieee1588 data sheet april 10, 2013 36 support@innovasic.com document #: ia211111101 - 0 4 1 - 505 - 883 - 5263 uncontrolled when pr inted or copied 1 - 888 - 824 - 4184 4.3 bga package physical dimensions figure 9 bga package physical dimensions
FIDO2100 3 - port industrial ethernet dlr switch with ieee1588 data sheet april 10, 2013 37 support@innovasic.com document #: ia211111101 - 0 4 1 - 505 - 883 - 5263 uncontrolled when pr inted or copied 1 - 888 - 824 - 4184 5 electrical characteristi cs tables 3 through 7 show the absolute maximum ratings, esd and latch - up characteristics, recommended operating conditions, dc characteristics of i/o cells and power consumption . table 3 absolute maximum ratings symbol parameter name conditions min typ max units vcck digital core supply voltage - 0.5 - 2.5 v vcc18a_pll pll analog supply voltage - 0.5 - 2.5 v vcc3io digital i/o supply voltage - 0.5 - 4.6 v vcc3o digital i/o supply voltage - 0.5 - 4.6 v t stg storage temperature - 65 - 150 o c t j operating junction temperature - 40 - 1 25 o c table 4 esd and latch - up characteristics symbol parameter name conditions min typ max units v hbm human body model 2000 v v mm machine model 200 v i latp positive latch - up 50 a i latn negative latch - up - 50 a table 5 recommended operating conditions symbol parameter name condit ions min typ max units vcck digital core supply voltage 1.62 1.8 1.98 v vcc18a_pll pll analog supply voltage 1.62 1.8 1.98 v vcc3io digital i/o supply voltage 3.0 3.3 3.6 v vcc3o digital i/o supply voltage 3.0 3.3 3.6 v t a ambient temperature - 40 - 85 o c sys_clk system clock - 25 - mhz table 6 dc characteristics of i/o cells symbol parameter name cond itions min typ max units v ih input high voltage 2.0 - - v v il input low voltage - - 0.8 v v oh output high voltage i oh = - 12 ma 2.4 - - v v ol output low voltage i ol = 12 ma - - 0.4 v r pu input pull - up resistance 40 75 190 k r pd input pull - down res istance 40 75 190 k c in input capacitance 2.4 pf
FIDO2100 3 - port industrial ethernet dlr switch with ieee1588 data sheet april 10, 2013 38 support@innovasic.com document #: ia211111101 - 0 4 1 - 505 - 883 - 5263 uncontrolled when pr inted or copied 1 - 888 - 824 - 4184 table 7 power consumption (nominal) i/o voltage 3.3vdc core voltage 1.8vdc pll voltage 1.8vdc total current power current power current power power 5.27ma 17.39mw 60.0ma 108.0mw .663ma 1.19mw 126.6mw 5.1 thermal characteristics the thermal resistance characteristics for the lqfp and the bga packages are prov ided in table 8 . all data is simulated based on the 2 s 2 p board type. the board type is defined by jedec standard jesd 51 - 7 for the pqfp package, and by jesd 51 - 9 for the bga package. table 8 thermal r esistance characteristics name des cription airflow (m/s) bga lqfp jc ( c/w) junction to case 0 8.03 17.5 ja ( c/w) junction to ambient 0 34.09 52.0 5.2 pll supply the pll for the FIDO2100 has dedicated supply and ground pins. for best performance of the pll it is desirable to provide a quiet or separate 1.8 v supply. decoupling capacitors of 0.1 uf and 10 uf should be placed on the board closely to the vdd18a_pll and gnda_pll pins. if the digital supply is to be used, it is best to also place a series fer rite bead before the decoupling capacitors and add additional decoupling capacitance of 0.1nf and 10nf. 5.3 system clock input the system clock input (sys_clk) requires a rail - to - rail clock input at 25 mhz. this 25 mhz cloc k input is then used by the pll the create the necessary internal clocks for the FIDO2100 .
FIDO2100 3 - port industrial ethernet dlr switch with ieee1588 data sheet april 10, 2013 39 support@innovasic.com document #: ia211111101 - 0 4 1 - 505 - 883 - 5263 uncontrolled when pr inted or copied 1 - 888 - 824 - 4184 5.4 reset: power - on - reset, hardware reset and software reset 5.4.1 power - on - reset the FIDO2100 has an internal power - on - reset (por) circuit which will provide a reset of the pll and the rst bit of the switch control register when vcck power is applied. the por circuit will keep the pll and rst bit in reset until the vcck power has exceeded a 1.2 v threshold. once the vcck voltage has exceeded the por threshold the pll will then need a minimum time of 60 n s to lock and provide a stable clock source. 5.4.2 hardware reset there is also a reset in put (reset_n) provided for a hardware reset of the FIDO2100 . when reset_n is asserted low the por circuit will reset the pll and the rst bit of the switch control register. the reset_n input must be asserted low for a minimum of 20 n s in order to assure a reset has occurred. on a reset, once the reset_n input has been de - asserted high, the pll will then need a minimum time of 60 n s to lock and provide a stable clock source. the reset_n input has an internal pull - up which is intended to prevent a reset if th e input is un - driven. 5.4.3 software reset software reset of the FIDO2100 is accomplished by writing a '1' to the rst bit of the switch control register. the rst bit is self - clearing on the next clock. when this bit is set, the control and status registers return to their default conditions. 5.5 test input the test input (test) should be tied low externally for normal operation. there are no user selectable tests. the test input has an internal pull - dow n which is intended to prevent a entering test mode if the input is un - driven.
FIDO2100 3 - port industrial ethernet dlr switch with ieee1588 data sheet april 10, 2013 40 support@innovasic.com document #: ia211111101 - 0 4 1 - 505 - 883 - 5263 uncontrolled when pr inted or copied 1 - 888 - 824 - 4184 6 host bus interface the host bus interface is used to read and/or write the various configuration and data registers within the FIDO2100 . th e host bus interface consists of the following inputs, an 8 - bit address bus (cpu_adrs[8:1]), a chip select (cpu_cs_n), a read select (cpu_rd_n) and a write select (cpu_wr_n), along with a 16 - bit bidirectional data bus (cpu_data[15:0]). 6.1 read, host bus interface a read is accomplished by selecting a register address using input cpu_adrs[8:1] , then asserting both cpu_cs_n and cpu_rd_n inputs for a sufficient time. the contents of the register read will be output on c pu_data[15:0] . the input cpu_wr_n must not be asserted during a read operation. a typical read operation, with necessary timing, can be seen below in f igure 1 0 . during the read operation the timing between cpu_cs_n and cpu_rd_n is not critical, however th e actual read cycle begins when both signals are asserted low with the last asserted signal determining the timing. the read cycle will end when either cpu_cs_n or cpu_rd_n are de - asserted high. in the timing diagram of f igure 1 0 , timing is shown only from cpu_rd_n for simplicity. figure 10 host interface, read timing table 9 host interface, read timing description symbol min max unit cpu_adrs setup time tadsu 0 ns cpu_adrs hold time tadhd 60 ns cpu_d ata valid time tdatval 60 ns cpu_data hold time tdathd 0 ns cpu_rd_n dead time trddt 40 ns
FIDO2100 3 - port industrial ethernet dlr switch with ieee1588 data sheet april 10, 2013 41 support@innovasic.com document #: ia211111101 - 0 4 1 - 505 - 883 - 5263 uncontrolled when pr inted or copied 1 - 888 - 824 - 4184 6.2 write, host bus interface a write is accomplished by selecting a register address using input cpu_adrs[8:1] , placing data on cpu_data[15:0] , and then asserting both cpu_cs_n and cpu_wr_n inputs for a sufficient time. the data on the cpu_data[15:0] bus will then be written to the selected register. the input cpu_rd_n must not be asserted during a write operation. a typi cal write operation, with necessary timing, can be seen below in f igure 11 . during the write operation the timing between cpu_cs_n and cpu_wr_n is not critical, however the actual write cycle begins when both signals are asserted low with the last asserted signal determining the timing. the write cycle will end when either cpu_cs_n or cpu_wr_n are de - asserted high. in the timing diagram of f igure 11 , timing is shown only from cpu_wr_n for simplicity. figure 11 host interface, wr ite timing table 10 host interface, write timing description symbol min max unit cpu_adrs setup time tadsu 0 ns cpu_adrs hold time tadhd 0 ns cpu_data setup time tdtsu 0 ns cpu_data hold time tdthd 0 ns cpu_wr_n write time twr 50 ns cpu_wr_n dead time twrdt 40 ns
FIDO2100 3 - port industrial ethernet dlr switch with ieee1588 data sheet april 10, 2013 42 support@innovasic.com document #: ia211111101 - 0 4 1 - 505 - 883 - 5263 uncontrolled when pr inted or copied 1 - 888 - 824 - 4184 7 external mii interface the two external ports, port 1 and port 2, of the 3 - port industrial ethernet switch are connected to their respective physical layer transceivers ( phy) through an ieee 802.3 media independent interface (mii). the mii interface is comprised of 16 pins: transmit clock (px_txc), transmit enable (px_txen), transmit error (px_txer), transmit data (px_txd[3:0]), receive clock (px_rxc), receive data valid ( px_rxdv), receive data error (px_rxer), receive data (px_rxd[3:0]), collision (px_col) and carrier sense (px_crs). 7.1 receive data, external mii interface an ether n et packet received by the phy will be t ransmitted to its respective port via an mii interface. the phy will transmit this data using the mii inputs: px_rxc , px_rxdv , px_rxer and px_rxd[3:0] . timing for the receive data is shown below in f igure 12 . figure 12 external m ii interface, receive data table 11 receive data, external mii interface description symbol min max unit receive data setup time trxdsu 10 ns receive data hold time trxdhd 10 ns receive data valid setup time trxdvsu 10 ns re ceive data valid hold time trxdvhd 10 ns receive data error setup time trxersu 10 ns receive data error hold time trxerhd 10 ns
FIDO2100 3 - port industrial ethernet dlr switch with ieee1588 data sheet april 10, 2013 43 support@innovasic.com document #: ia211111101 - 0 4 1 - 505 - 883 - 5263 uncontrolled when pr inted or copied 1 - 888 - 824 - 4184 7.2 transmit data, external mii interface an ethernet packet to be tran smitted will be sent to its respective phy via an mii interface. the phy will transmit this data using the mii inputs: px_txc , px_txen , px_txer and px_txd[3:0] . timing for the transmit data is shown below in f igure 13 . figure 13 external mii interface, transmit data table 12 transmit data, external mii interface description symbol min max unit transmit data valid time ttxdval 15 ns transmit data hold time ttxdhd 0 ns transmit data enable valid time tt xenval 15 ns transmit data valid hold time ttcenhd 0 ns transmit data error valid time ttxerval 15 ns transmit data error hold time ttxerhd 0 ns 8 internal mii interface the single internal port, port cpu , of t he 3 - port industrial ethernet switch acts as a physical layer transceivers (phy) media independent interface (mii). this mii interface is comprised of 16 pins: transmit clock (cpu_txc), transmit enable (cpu_txen), transmit error (cpu_txer), transmit data ( cpu_txd[3:0]), receive clock (cpu_rxc), receive data valid (cpu_rxdv), receive data error (cpu_rxer), receive data (cpu_rxd[3:0]), collision (cpu_col) and carrier sense (cpu_crs). however, as the internal mii interface always runs at 100mb and full - duplex, the output cpu_col is always low and the output cpu_crs is the same as cpu_rxdv .
FIDO2100 3 - port industrial ethernet dlr switch with ieee1588 data sheet april 10, 2013 44 support@innovasic.com document #: ia211111101 - 0 4 1 - 505 - 883 - 5263 uncontrolled when pr inted or copied 1 - 888 - 824 - 4184 8.1 receive data, internal mii interface an ethernet packet received by the phy will be transmitted to its respective port v ia an mii interface. the phy will transmit this data using the mii inputs: px_rxc , px_rxdv , px_rxer and px_rxd[3:0] . timing for the receive data is shown below in f igure 14 . figure 14 internal mii interface, receive data table 13 receive data, external mii interface description symbol min max unit receive data setup time ttxdsu 10 ns receive data hold time ttxdhd 10 ns receive data enable setup time ttxensu 10 ns receive data enable hold time ttxe nhd 10 ns receive data error setup time ttxersu 10 ns receive data error hold time ttxerhd 10 ns
FIDO2100 3 - port industrial ethernet dlr switch with ieee1588 data sheet april 10, 2013 45 support@innovasic.com document #: ia211111101 - 0 4 1 - 505 - 883 - 5263 uncontrolled when pr inted or copied 1 - 888 - 824 - 4184 8.2 transmit data, internal mii interface an ethernet packet to be transmitted will be sent to its respective phy via an mii interface. the phy will transmit this data using the mii inputs: px_txc , px_txen , px_txer and px_txd[3:0] . timing for the transmit data is shown below in f igure 15 . figure 15 internal mii interface, tra nsmit data table 14 transmit data, external mii interface description symbol min max unit transmit data valid time trxdval 5 ns transmit data hold time trxdhd 0 ns transmit data valid valid time trxdvval 5 ns transmit data valid hold time trxdvhd 0 ns transmit data error valid time trxerval 5 ns transmit data error hold time trxerhd 0 ns
FIDO2100 3 - port industrial ethernet dlr switch with ieee1588 data sheet april 10, 2013 46 support@innovasic.com document #: ia211111101 - 0 4 1 - 505 - 883 - 5263 uncontrolled when pr inted or copied 1 - 888 - 824 - 4184 9 control and status registers table 13 below contains a listing of all control & stat us registers accessible from the host bus interface. the table includes the address, register name, a register mnemonic and the read/write status of the register. a detailed explanation of the register s is also included in this section following the table . 9.1 register map table 15 register map address offset (cpu_adrs[ 8:0 ]) function mnemonic r/w 0 x 00 time sync control ts_control r/w 0 x 02 time sync irq event t s_event r/w 0 x 04 addend_low addend_lo r/w 0 x 06 addend_high addend_hi r/w 0 x 08 accumulator_low accum_lo r/w 0 x 0 a accumulator_high accum_hi r/w 0 x 0 c systemtime_low_low systime_lo_lo r/w 0 x 0 e systemtime_low_high systime_lo_hi r/w 0 x 10 systemtime_high_l ow systime_hi_lo r/w 0 x 12 systemtime_high_high systime_hi_hi r/w 0 x 14 targettime 1 _low_low tgttim 1 _lo_lo r/w 0 x 16 targettime 1 _low_high tgttim 1 _lo_hi r/w 0 x 18 targettime 1 _high_low tgttim 1 _hi_lo r/w 0 x 1 a targettime 1 _high - high tgttim 1 _hi_hi r/w 0 x 1 c targ ettime 2 _low_low tgttim 2 _lo_lo r/w 0 x 1 e targettime 2 _low_high tgttim 2 _lo_hi r/w 0 x 20 targettime 2 _high_low tgttim 2 _hi_lo r/w 0 x 22 targettime 2 _high_high tgttim 2 _hi_hi r/w 0 x 24 event 1 snap_low_low evnt 1 _lo_lo r
FIDO2100 3 - port industrial ethernet dlr switch with ieee1588 data sheet april 10, 2013 47 support@innovasic.com document #: ia211111101 - 0 4 1 - 505 - 883 - 5263 uncontrolled when pr inted or copied 1 - 888 - 824 - 4184 address offset (cpu_adrs[ 8:0 ]) function mnemonic r/w 0 x 26 event 1 snap_low_high evnt 1 _lo_hi r 0 x 28 e vent 1 snap_high_low evnt 1 _hi_lo r 0 x 2 a event 1 snap_high_high evnt 1 _hi_hi r 0 x 2 c event 2 snap_low_low evnt 2 _lo_lo r 0 x 2 e event 2 snap_low_high evnt 2 _lo_hi r 0 x 30 event 2 snap_high_low evnt 2 _hi_lo r 0 x 32 event 2 snap_high_high evnt 2 _hi_hi r 0 x 34 xmit_snapshot_lo w_low txts_lo_lo r 0 x 36 xmit_snapshot_low_high txts_lo_hi r 0 x 38 xmit_snapshot_high_low txts_hi_lo r 0 x 3 a xmit_snapshot_high_high txts_hi_hi r 0 x 3 c recv_snapshot_low_low rxts_lo_lo r 0 x 3 e recv_snapshot_low_high rxts_lo_hi r 0 x 40 recv_snapshot_high_lo w rxts_hi_lo r 0 x 42 recv_snapshot_high_high rxts_hi_hi r 0 x 44 recv_sourceid_low_low rxid_lo_lo r 0 x 46 recv_sourceid_low_high rxid_lo_hi r 0 x 48 recv_sourceid_high_low rxid_hi_lo r 0 x 4 a recv_sourceid_high_high rxid_hi_hi r 0 x 4 c recv_sequenceid rxseqid r 0 x 4 e ptp sub - domain subdomain r/w 0 x 50 switch control sw_control r/w 0 x 52 switch irq event sw_event r/w 0 x 54 switch irq mask sw_mask r/w 0 x 56 port 1 seed prt 1 seed r/w 0 x 58 port 2 seed prt 2 seed r/w 0 x 5 a macaddress_low_low mac_lo_lo r/w
FIDO2100 3 - port industrial ethernet dlr switch with ieee1588 data sheet april 10, 2013 48 support@innovasic.com document #: ia211111101 - 0 4 1 - 505 - 883 - 5263 uncontrolled when pr inted or copied 1 - 888 - 824 - 4184 address offset (cpu_adrs[ 8:0 ]) function mnemonic r/w 0 x 5 c macadd ress_low_high mac_lo_hi r/w 0 x 5 e macaddress_high_low mac_hi_lo r/w 0 x 60 multicast_hash_filter_index mchfi r/w 0 x 62 multicast_hash_filter_value mchfv r/w 0 x 64 free_running_timer_low freetmr_lo r 0 x 66 free_running_timer_high freetmr_hi r 0 x 68 pit_timeo ut_low pittmo_lo r 0 x 6 a pit_timeout_high pittmo_hi r 0 x 6 c redundancy control rdndnc_control r/w 0 x 6 e ring beacon state rng_bcnstate r 0 x 70 beacon_timeout_low bcntmo_lo r/w 0 x 72 beacon_timeout_high bcntmo_hi r/w 0 x 74 port 1 _recv_beacon_ts_low p1bcnts_l o r 0 x 76 port 1 _recv_beacon_ts_high p 1 bcnts_hi r 0 x 78 port 2 _recv_beacon_ts_low p 2 bcnts_lo r 0 x 7 a port 2 _recv_beacon_ts_high p 2 bcnts_hi r 0 x 7 c port 1 _neighbor_check_srcid_low_low p 1 nchksid_lo_lo r 0 x 7 e port 1 _neighbor_check_srcid_low_high p 1 nchksid_lo_hi r 0 x 80 port 1 _neighbor_check_srcid_high_low p 1 nchksid_hi_lo r 0 x 82 port 2 _neighbor_check_srcid_low_low p 2 nchksid_lo_lo r 0 x 84 port 2 _neighbor_check_srcid_low_high p 2 nchksid_lo_hi r 0 x 86 port 2 _neighbor_check_srcid_high_low p 2 nchksid_hi_lo r 0 x 88 port1_neig hbor_status_srcid_low_low p 1 nstssid_lo_lo r 0 x 8 a port 1 _neighbor_status_srcid_low_high p 1 nstssid_lo_hi r 0 x 8 c port 1 _neighbor_status_srcid_high_low p 1 nstssid_hi_lo r 0 x 8 e port 2 _neighbor_status_srcid_low_low p 2 nstssid_lo_lo r 0 x 90 port2_neighbor_status_sr cid_low_high p 2 nstssid_lo_hi r
FIDO2100 3 - port industrial ethernet dlr switch with ieee1588 data sheet april 10, 2013 49 support@innovasic.com document #: ia211111101 - 0 4 1 - 505 - 883 - 5263 uncontrolled when pr inted or copied 1 - 888 - 824 - 4184 address offset (cpu_adrs[ 8:0 ]) function mnemonic r/w 0 x 92 port 2 _neighbor_status_srcid_high_low p 2 nstssid_hi_lo r 0 x 94 ring_supervisor_macid_low_low rngsprvsrid_lo_lo r/w 0 x 96 ring_supervisor_macid_low_high rngsprvsrid_lo_hi r/w 0 x 98 ring_supervisor_macid_high_low rngsprvsri d_hi_lo r/w 0 x 9 a reserved r 0 x 9 c port 1 _recv_group_frame_count p 1 rxgrpfrmcnt r 0 x 9 e port 2 _recv_group_frame_count p 2 rxgrpfrmcnt r 0 xa 0 port 1 _recv_unicast_frame_count p 1 rxunifrmcnt r 0 xa 2 port 2 _recv_unicast_frame_count p 2 rxunifrmcnt r 0 xa 4 port1_recv_b yte_count_low p 1 rxbytcnt_lo r 0 xa 6 port 1 _recv_byte_count_high p 1 rxbytcnt_hi r 0 xa 8 port 2 _recv_byte_count_low p 2 rxbytcnt_lo r 0 xaa port 2 _recv_byte_count_high p 2 rxbytcnt_hi r 0 xac port 1 _recv_large_error_frame_count p 1 rxlrgfrmcnt r 0 xae port2_recv_large_ error_frame_count p 2 rxlrgfrmcnt r 0 xb 0 port 1 _recv_align_error_frame_count p 1 rxalnfrmcnt r 0 xb 2 port 2 _recv_align_error_frame_count p 2 rxalnfrmcnt r 0 xb 4 port 1 _recv_fcs_error_frame_count p 1 rxfcsfrmcnt r 0 xb 6 port 2 _recv_fcs_error_frame_count p 2 rxfcsfrmcnt r 0 xb 8 port 1 _recv_error_frame_count p 1 rxerrfrmcnt r 0 xba port 2 _recv_error_frame_count p 2 rxerrfrmcnt r 0 xbc port 1 _xmit_group_frame_count p 1 txgrpfrmcnt r 0 xbe port 2 _xmit_group_frame_count p 2 txgrpfrmcnt r 0 xc 0 port 1 _xmit_unicast_frame_count p1txunifrmcnt r 0 xc 2 port 2 _xmit_unicast_frame_count p 2 txunifrmcnt r 0 xc 4 port 1 _xmit_byte_count_low p 1 txbytcnt_lo r 0 xc 6 port 1 _xmit_byte_count_high p 1 txbytcnt_hi r
FIDO2100 3 - port industrial ethernet dlr switch with ieee1588 data sheet april 10, 2013 50 support@innovasic.com document #: ia211111101 - 0 4 1 - 505 - 883 - 5263 uncontrolled when pr inted or copied 1 - 888 - 824 - 4184 address offset (cpu_adrs[ 8:0 ]) function mnemonic r/w 0 xc 8 port 2 _xmit_byte_count_low p 2 txbytcnt_lo r 0 xca port 2 _xmit_byte_count_high p 2 txbytcnt_hi r 0 xcc port 1 _xmit_single_collision_frame_count p 1 txsclfrmcnt r 0 xce port 2 _xmit_single_collision_frame_count p 2 txsclfrmcnt r 0 xd 0 port 1 _xmit_multi_collision_frame_count p 1 txmclfrmcnt r 0 xd 2 port 2 _xmit_multi_collision_frame_count p 2 txmclfrmcnt r 0 xd 4 port1_xmit _excess_collision_frame_count p 1 txxclfrmcnt r 0 xd 6 port 2 _xmit_excess_collision_frame_count p 2 txxclfrmcnt r 0 xd 8 port 1 _xmit_error_frame_count p 1 txerrfrmcnt r 0 xda port 2 _xmit_error_frame_count p 2 txerrfrmcnt r 0 xdc beacon_generation_control bcngencntrl r/ w 0 xde beacon_interval_low bcnintrvl_lo r/w 0 xe 0 beacon_interval_high bcnintrvl_hi r/w 0 xe 2 beacon_data_index bcndataidx r/w 0 xe 4 beacon_data_value bcndataval r/w 0 xe 6 embedded_switch_version embswtchver r
FIDO2100 3 - port industrial ethernet dlr switch with ieee1588 data sheet april 10, 2013 51 support@innovasic.com document #: ia211111101 - 0 4 1 - 505 - 883 - 5263 uncontrolled when pr inted or copied 1 - 888 - 824 - 4184 9.2 detailed register explanations 9 . 2.1 time sync control register mnemonic type offset bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ts_control r/w 0 x 00 rxm txm mm ppse tte 2 tte 1 evm 2 evm 1 ttm 2 ttm 1 power - up defaults 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ttm1 - 2 target time interrupt mask 1 - 2 . the target time interrupt mask 1 - 2 controls whether the corresponding target time interrupt is passed to the host processor. when any of these bits are set, the cor responding interrupt to the host is enabled. when any of these bits are cleared, the corresponding target time interrupt to the host is disabled. evm1 event 1 interrupt mask . the interrupt for the host is always disabled, regardless of the state of this bi t. evm2 event 2 interrupt mask . the interrupt for the host is always disabled, regardless of the state of this bit. tte1 - 2 target time interrupt enable 1 - 2 . the target time interrupt enable 1 - 2 controls whether the corresponding target time interrupt is e nabled. when any of these bits are set, the corresponding target time register is compared with system time register. when they match, the corresponding ttp1 - 2 bit in ts_event register is set and the corresponding tte1 - 2 bit is reset. if the correspondin g ttm1 - 2 bit is also set then an interrupt is delivered to the host. to prevent spurious interrupts firmware should write to target time registers 1 - 2, only when corresponding tte1 - 2 is not set. ppse pulse per second enable . when this bit is set, the s tate of ttp2 bit in the ts_event register is reflected on output pin pps_sig . mm master mode . when this bit is set, the time sync logic implementing ieee 1588 ordinary clock hardware assist on the local port connected to the host cpu mii interface, wil l operate in master mode. when this bit is reset the same logic will operate in slave mode. txm transmit snapshot interrupt mask . the transmit snapshot interrupt mask controls whether the transmit snapshot txs bit in the ts_event register, should interr upt the host processor. when this bit is set, the interrupt to the host is enabled. when cleared, the interrupt to the host is disabled.
FIDO2100 3 - port industrial ethernet dlr switch with ieee1588 data sheet april 10, 2013 52 support@innovasic.com document #: ia211111101 - 0 4 1 - 505 - 883 - 5263 uncontrolled when pr inted or copied 1 - 888 - 824 - 4184 rxm receive snapshot interrupt mask . the receive snapshot interrupt mask controls whether the receive snapshot rxs b it in the ts_event register, should interrupt the host processor. when this bit is set, the interrupt to the host is enabled. when cleared, the interrupt to the host is disabled. 9 . 2.2 time sync interr upt event register mnemonic type offset bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ts_event r/w 0 x 02 rxs txs evs 2 evs 1 ttp 2 ttp 1 power - up defaults 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 all interrupt requests from time sync event register will be d elivered to the host cpu through the ts_event_irq_n signal. ttp1 - 2 target time interrupt pending 1 - 2 . the target time interrupt pending 1 - 2 indicates if the corresponding target time register matched the system time, as explained under tte1 - 2 in the time sync control register. if corresponding ttm1 - 2 bit in the time sync control register is also set, an interrupt will be delivered to the host. ttp1 - 2 can be reset by writing a 1 to it. evs1 event 1 snapshot . a rising edge on the input pin event_1_sig causes a snapshot of the system time to be saved in the external event 1 snapshot register, and the evs1 bit to be set. after an event_1_sig, polling of this register should take place in order to determine that a snapshot has taken place when evs1 is set . now the external event 1 snapshot register can be read. a subsequent rising edge will not cause the snapshot to be updated while the evs1 bit is set. this bit can be reset by writing a 1 to it. evs2 event 2 snapshot . a rising edge on the input pin e vent_2_sig causes a snapshot of the system time to be saved in the external event 2 snapshot register, and the evs2 bit to be set. after an event_2_sig, polling of this register should take place in order to determine that a snapshot has taken place when evs2 is set. now the external event 2 snapshot register can be read. a subsequent rising edge will not cause the snapshot to be updated while the evs2 bit is set. this bit can be reset by writing a 1 to it. txs transmit snapshot . a sync frame in master mode or delay_req frame in slave mode will cause a snapshot of the system time to be saved in the transmit snapshot register and the txs bit to be set. subsequent sync/delay_req frames will not cause the snapshot to be updated while the
FIDO2100 3 - port industrial ethernet dlr switch with ieee1588 data sheet april 10, 2013 53 support@innovasic.com document #: ia211111101 - 0 4 1 - 505 - 883 - 5263 uncontrolled when pr inted or copied 1 - 888 - 824 - 4184 txs bit is set. if this bit is set and the txm bit in ts_control register is also set, an interrupt will be delivered to the host. this bit can be reset by writing a 1 to it. rxs receive snapshot . a sync frame in slave mode or a delay_req frame in master mode will cau se a snapshot of the system time to be saved in the receive snapshot register, the source id/sequence id of incoming frame to be saved in the receive source id/sequence id registers and the rxs bit to be set. up to 16 snapshots will be stored in the fifo if firmware is slow to process them. if the fifo is full, subsequent sync/delay_req frames will not cause a snapshot/source id/sequence id to be stored. if this bit is set and the rxm bit in ts_control register is also set, an interrupt will be delivered to the host. this bit can be reset by writing a 1 to it. if the bit doesnt reset, it indicates additional snapshots are present. firmware should repeatedly read and store all entries from the fifo until this bit is reset. 9 . 2.3 addend register mnemonic type offset bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 addend_lo r/w 0 x 04 addend[ 15:0 ] power - up defaults 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 mnemonic type offset bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 addend_hi r/w 0 x 06 addend[ 31:16 ] power - up defaults 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 the addend register consists of two 16 - bit registers. the addend register contains the frequency scaling value used by a firmware algorithm to achieve time synchronization in the mo dule. the value in this register is added to the value in the accumulator. when the accumulator rolls over, an overflow pulse is asserted and increments system time. because the addend register is cleared at reset, it must be written with a non - zero value to allow system time to increment. reads of the two 16 - bit registers can be performed in any order. when performing writes, addend_lo should be written first. when addend_hi is written later, an internal addend register will be updated with the full 32 - bit value.
FIDO2100 3 - port industrial ethernet dlr switch with ieee1588 data sheet april 10, 2013 54 support@innovasic.com document #: ia211111101 - 0 4 1 - 505 - 883 - 5263 uncontrolled when pr inted or copied 1 - 888 - 824 - 4184 9 . 2.4 accumulator register mnemonic type offset bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 accum_lo r/w 0 x 08 accumulator [ 15:0 ] power - up defaults 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 mnemonic type offset bi ts 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 accum_hi r/w 0 x 0 a accumulator [ 31:16 ] power - up defaults 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 the accumulator register consists of two 16 - bit registers. the accumulator register serves as a precision frequency divide r in the time synchronization logic. firmware calculates a frequency scaling value to be written to the addend register. the data in the accumulator register is added to the value in the addend register once every period of the system clock. when the accum ulator rolls over, an overflow pulse is asserted which increments the value in the system timer. this register is not read or written to in normal operation. when performing reads, accum_lo should be read first, which will cause the higher 16 bits of the i nternal accumulator register to be latched and when accum_hi is read later, the latched value will be returned. when performing writes, accum_lo should be written first and when accum _hi is written later, the internal accumulator register will be updated with the full 32 - bit value. 9 . 2.5 system time register mnemonic type offset bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 systime_lo_lo r/w 0 x 0 c systime [ 15:0 ] power - up defaults 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 mne monic type offset bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 systime_lo_hi r/w 0 x 0 e systime [ 31:16 ] power - up defaults 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 mnemonic type offset bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 systime_hi_lo r/w 0 x 10 systime [47:3 2 ] power - up defaults 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 mnemonic type offset bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 systime_hi_hi r/w 0 x 12 systime [ 63:48 ] power - up defaults 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
FIDO2100 3 - port industrial ethernet dlr switch with ieee1588 data sheet april 10, 2013 55 support@innovasic.com document #: ia211111101 - 0 4 1 - 505 - 883 - 5263 uncontrolled when pr inted or copied 1 - 888 - 824 - 4184 the system time register consists of four 16 - bit registers. the system timer is a loadable up - counter and reflects the local time in the module. the system timer is incremented when the accumulator register rolls over. when performing reads, systime_lo_lo should be read first, which will cause th e higher 48 - bits of the internal system time register to be latched. when other systime_xx_xx registers are read later, the latched value will be returned. when performing writes, the lower three systime_xx_xx should be written first, and when systime_hi_h i is written later, the internal system time register will be updated with the full 64 bit value. 9 . 2.6 target time1 register mnemonic type offset bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 tgttim 1 _lo_lo r/w 0 x 14 target1 [ 15:0 ] power - up defaults 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 mnemonic type offset bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 tgttim 1 _lo_hi r/w 0 x 16 target1 [ 31:16 ] power - up defaults 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 mnemonic type offset bits 15 1 4 13 12 11 10 9 8 7 6 5 4 3 2 1 0 tgttim 1 _hi_lo r/w 0 x 18 target1 [ 47:32 ] power - up defaults 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 mnemonic type offset bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 tgttim 1 _hi_hi r/w 0 x 1 a target1 [ 63:48 ] power - up defaults 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 the target time1 register consists of four 16 - bit registers. when the system time is equal to the target time value, the ttp1 bit in the time sync event register is set and an interrupt is generated to the host if the ttm1 bit in the time sync control register is also set. reads and writes of four 16 - bit registers can be performed in any order. in order to prevent spurious interrupts during writes, the tte1 bit should be 0 in the time sync control register when writing to any of the four 16 - bit registers.
FIDO2100 3 - port industrial ethernet dlr switch with ieee1588 data sheet april 10, 2013 56 support@innovasic.com document #: ia211111101 - 0 4 1 - 505 - 883 - 5263 uncontrolled when pr inted or copied 1 - 888 - 824 - 4184 9 . 2.7 target time2 register mnemonic type offset bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 tgttim 2 _lo_lo r/w 0 x 1 c target2 [ 15:0 ] power - up defaults 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 mnemonic type offset bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 tgttim 2 _lo_hi r/w 0 x 1 e target2 [ 31:16 ] power - up defaults 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 mnemonic type offset bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 tgttim 2 _hi_lo r/w 0 x 20 target 2 [ 47:32 ] power - up defaults 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 mnemonic type offset bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 tgttim 2 _hi_hi r/w 0 x 22 target2 [ 63:48 ] power - up defaults 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 the target time2 register consists of four 16 - bit registers. when the system time is equal to the target time value, the ttp2 bit in the time sync event register is set and an interrupt is generated to the host if the ttm2 bit in the time sync control register is also set. reads and writes of four 16 - bit registers can be performed in any order. in order to prevent spurious interrupts during writes, the tte2 bit should be 0 in the time sync control register when writing to any of the four 16 - bit registers. as explained under the ppse bit i n time sync control register, the target time2 register can also be used to generate a pulse per second output on the pps_sig pin. 9 . 2.8 external event 1 snapshot register mnemonic type offset bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 evnt 1 _lo_lo r 0 x 24 evnt1snap [ 15:0 ] power - up defaults 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 mnemonic type offset bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 evnt 1 _lo_hi r 0 x 26 evnt1snap [ 31:16 ] power - up defaults 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
FIDO2100 3 - port industrial ethernet dlr switch with ieee1588 data sheet april 10, 2013 57 support@innovasic.com document #: ia211111101 - 0 4 1 - 505 - 883 - 5263 uncontrolled when pr inted or copied 1 - 888 - 824 - 4184 mnemonic type offset bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 evnt 1 _hi_lo r 0 x 28 evnt1snap [ 47:32 ] power - up defaults 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 mnemonic type offset bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 evnt1 _hi_hi r 0 x 2 a evnt1snap [ 63:48 ] power - up defaults 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 the external event 1 snapshot register consists of four 16 - bit registers. a rising edge on the input signal event_1_sig , triggers a snapshot of the system time into evnt 1_xx_xx registers and the evs1 bit in time sync event register is set. polling of the time sync event register for evs1 can be used to determine when this register is ready for a read. reads of the four 16 - bit registers can be performed in any order. the evs1 bit in the time sync event register must be reset by writing a 1 to it in order to snapshot the system time at the next rising edge of event_1_sig . 9 . 2.9 external event 2 snapshot register mne monic type offset bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 evnt 2 _lo_lo r 0 x 2 c evnt2snap [ 15:0 ] power - up defaults 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 mnemonic type offset bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 evnt 2 _lo_hi r 0 x 2 e evnt2snap [ 31:16 ] p ower - up defaults 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 mnemonic type offset bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 evnt 2 _hi_lo r 0 x 30 evnt2snap [ 47:32 ] power - up defaults 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 mnemonic type offset bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 evnt 2 _hi_hi r 0 x 32 evnt2snap [ 63:48 ] power - up defaults 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
FIDO2100 3 - port industrial ethernet dlr switch with ieee1588 data sheet april 10, 2013 58 support@innovasic.com document #: ia211111101 - 0 4 1 - 505 - 883 - 5263 uncontrolled when pr inted or copied 1 - 888 - 824 - 4184 the external event 2 snapshot register consists of four 16 - bit registers. a rising edge on the input signal event_2_sig , triggers a snapshot of t he system time into evnt2_xx_xx registers and the evs2 bit in time sync event register is set. polling of the time sync event register for evs2 can be used to determine when this register is ready for a read. reads of the four 16 - bit registers can be perf ormed in any order. the evs2 bit in the time sync event register must be reset by writing a 1 to it in order to snapshot the system time at the next rising edge of event_2_sig . 9 . 2.10 transmit snapshot re gister mnemonic type offset bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 txts_lo_lo r 0 x 34 transmitsnap [ 15:0 ] power - up defaults 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 mnemonic type offset bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 txts_lo_hi r 0 x 36 transmit snap [ 31:16 ] power - up defaults 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 mnemonic type offset bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 txts_hi_lo r 0 x 38 transmitsnap [ 47:32 ] power - up defaults 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 mnemonic type offset bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 txts_hi_hi r 0 x 3 a transmitsnap [ 63:48 ] power - up defaults 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 the transmit snapshot register consists of four 16 - bit registers. a sync frame in master mode or delay_req frame in slave mode tr iggers a snapshot of the system time into xmit_xx_xx registers and the txs bit in time sync event register is set. reads of the four 16 - bit registers can be performed in any order. the txs bit in the time sync event register must be reset by writing a 1 to it in order to snapshot system time at the next sync or delay_req frame. 9 . 2.11 receive snapshot register mnemonic type offset bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rxts_lo_lo r 0 x 3 c receivesnap [15 : 0 ] power - up defaults 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
FIDO2100 3 - port industrial ethernet dlr switch with ieee1588 data sheet april 10, 2013 59 support@innovasic.com document #: ia211111101 - 0 4 1 - 505 - 883 - 5263 uncontrolled when pr inted or copied 1 - 888 - 824 - 4184 mnemonic type offset bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rxts_lo_hi r 0 x 3 e receivesnap [ 31:16 ] power - up defaults 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 mnemonic type offset bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rxts_hi_lo r 0 x 40 receivesnap [ 47:32 ] power - up defaults 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 mnemonic type offset bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rxts_hi_hi r 0 x 42 receivesnap [ 63:48 ] power - up defaults 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 the receive snapshot register consists of four 16 - bit registers. a sync frame in slave mode or delay_req frame in master mode triggers a snapshot of the system time into the recv_xx_xx registers and the rxs bit in time sync event register is set. reads of four 16 - bit registers can be performed in any order. up to 16 snapshots will be stored in the fifo if firmware is slow to process them. if the fifo is full, subsequent sync/delay_req frames will not cause the snapshot/source id/sequence i d to be stored. the rxs bit in the time sync event register must be reset by writing a 1 to it after reading a snapshot. if the bit doesnt reset, it indicates that additional snapshots are present. firmware should repeatedly read and store all entries from the fifo until this bit is reset. 9 . 2.12 receive source id register mnemonic type offset bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rxid_lo_lo r 0 x 44 sourceid [ 15:0 ] power - up defaults 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 mnemonic type offset bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rxid_lo_hi r 0 x 46 sourceid [ 31:16 ] power - up defaults 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 mnemonic type offset bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rxid_hi_lo r 0 x 48 sourceid [ 47:32 ] power - up defaults 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
FIDO2100 3 - port industrial ethernet dlr switch with ieee1588 data sheet april 10, 2013 60 support@innovasic.com document #: ia211111101 - 0 4 1 - 505 - 883 - 5263 uncontrolled when pr inted or copied 1 - 888 - 824 - 4184 mnemonic type offset bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rxid_hi_hi r 0 x 4 a sourceid [ 63:48 ] power - up defaults 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 the receive source id register c onsists of four 16 - bit registers. the reception of a sync frame in slave mode or delay_req frame in master mode triggers the capture of the source id field in the received frame into the rxid_xx_xx registers. reads of the four 16 - bit registers can be perfo rmed in any order. see the receive snapshot register for additional description. 9 . 2.13 receive sequence id register mnemonic type offset bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rxseqid r 0 x 4 c sequence id [ 15:0 ] power - up defaults 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 the reception of a sync frame in slave mode or delay_req frame in master mode triggers the capture of the sequence id field in the received frame into the rxseqid register. see the receive snap shot register for additional description. 9 . 2.14 ptp sub - domain register mnemonic type offset bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 subdomain r/w 0 x 4 e subdomain[ 7:0 ] power - up defaults 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 the ptp sub - domain register is used to specify the sub - domain field of ptp event frames. only the ptp event frames matching the value in this register will be time stamped. by default, this register will be 0, matching only the defa ult sub - domain event frames. 9 . 2.15 switch control register mnemonic type offset bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 sw_control r/w 0 x 50 ulfe dms dbs dfc dbg p 2 ly p 1 ly p 2 lo p 1 lo p 2 s p 1 s p 2 h p 1 h p 2 r p 1 r rst power - up defaults 1 1 0 0 0 0 0 0 0 0 0 0 0 1 1 0 rst chip reset . when a 1 is written to this bit, all logic is returned to the same default state as when a power - on reset occurs. this bit is self - clearing.
FIDO2100 3 - port industrial ethernet dlr switch with ieee1588 data sheet april 10, 2013 61 support@innovasic.com document #: ia211111101 - 0 4 1 - 505 - 883 - 5263 uncontrolled when pr inted or copied 1 - 888 - 824 - 4184 p1r port 1 reset . when this bit is set , port 1 is held in reset and no packets will be transmitted or received on port 1. this bit must be set for a minimum of 500 nanosecs for a proper reset. p2r port 2 reset . when this bit is set, port 2 is held in reset and no packets will be transmitted o r received on port 2. this bit must be set for a minimum of 500 nanosecs for a proper reset. p1h port 1 half duplex . when this bit is set, port 1 is in half duplex mode. when this bit is reset, port 1 is in full duplex mode. this bit should be set to the same duplex mode as negotiated/forced in the phy. this bit should be changed only when p1r is set i.e. port 1 is held in reset. p2h port 2 half duplex . when this bit is set, port 2 is in half duplex mode. when this bit is reset, port 2 is in full duplex mode. this bit should be set to the same duplex mode as negotiated/forced in the phy. this bit should be changed only when p2r is set i.e. port 2 is held in reset. p1s port 1 speed 10mbps . when this bit is set, the port 1 is operating at 10mbps speed. wh en this bit is reset, port 1 is operating at 100mbps speed. this bit should be set to the same speed as negotiated/forced in the phy. this bit should be changed only when p1r is set i.e. port 1 is held in reset. p2s port 2 speed 10mbps . when this bit is set, the port 2 is operating at 10mbps speed. when this bit is reset, port 2 is operating at 100mbps speed. this bit should be set to the same speed as negotiated/forced in the phy. this bit should be changed only when p2r is set i.e. port 2 is held in re set. p1lo port 1 led on . when this bit is set, the port 1 led is turned on. when there is no link activity on port 1 the led will be solid indicating the link is up. when there is link activity on port 1 the led will blink at a rate of 10hz. firmware can place port 1 in reset and set this bit to test the led. p2lo port 2 led on . when this bit is set, the port 2 led is turned on. when there is no link activity on port 2, the led will be solid indicating the link is up. when there is link activity on port 2 the led will blink at a rate of 10hz. firmware can place port 2 in reset and set this bit to test the led. p1ly port 1 led yellow . when this bit is set, the port 1 led will be driven to the yellow color. if this bit is reset, the port 1 led will be drive n to the green color. firmware can place port 1 in reset and set/reset this bit to test yellow/green color leds.
FIDO2100 3 - port industrial ethernet dlr switch with ieee1588 data sheet april 10, 2013 62 support@innovasic.com document #: ia211111101 - 0 4 1 - 505 - 883 - 5263 uncontrolled when pr inted or copied 1 - 888 - 824 - 4184 p2ly port 2 led yellow . when this bit is set, the port 2 led will be driven to the yellow color. if this bit is reset, the port 2 led will be driven to the green color. firmware can place port 2 in reset and set/reset this bit to test yellow/green color leds. dbg internal port debug mode . when this bit is set, the internal port connected to the host cpu will operate in promiscuous mode and will forward all traffic received on ports 1 and 2 to host cpu. when the combined traffic received on ports 1 and 2 exceed the bandwidth capacity of 100mbps of the internal port, frames will be dropped on the internal port. hence this setting must be used only for debug purposes and not during normal operation. dfc disable flow control . when this bit is set, flow control is disabled on all ports in both full and half duplex modes. dbs disable broadcast storm control . when this bit is set, broadcast storm cont rol will be disabled. dms disable multicast storm control . when this bit is set multicast storm control will be disabled. ulfe unicast mac address learning and filtering enable . when this bit is set, dynamic unicast mac address learning and filtering is enabled. to flush unicast mac address learning table reset this bit and then set it again. 9 . 2.16 switch irq event register mnemonic type offset bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 sw_event r/w 0 x 52 ls t 2 lst 1 pit p 2 l p 1 l bto 2 bto 1 brx 2 brx 1 rbs 2 rbs 1 lirq 2 lirq 1 power - up defaults 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 all interrupt requests from the switch irq event register will be delivered to the host cpu through the sw_event_irq_n signal. lirq1 port 1 link status change irq . when a change of status occurs on the lst1 bit, then the lirq1 will be set. when the l1m bit in the switch mask register is also set, then an interrupt is delivered to the host cpu. this bit can be reset by writing a 1 to it. lirq2 port 2 link status change irq . when a change of status occurs on the lst2 bit, then the lirq2 will be set. when the l2m bit in the switch mask register is
FIDO2100 3 - port industrial ethernet dlr switch with ieee1588 data sheet april 10, 2013 63 support@innovasic.com document #: ia211111101 - 0 4 1 - 505 - 883 - 5263 uncontrolled when pr inted or copied 1 - 888 - 824 - 4184 also set, then an interrupt is delivered to the host cpu. this bit can be reset by writing a 1 to it. rbs1 port 1 ring beacon state change irq . when a ring beacon is received through port 1 and a change of state field in the frame is detected when compared to the previous beacon, this bit is set. when the rbm1 bit in the switch mask register is also set, an interrupt is delivered to the host cpu. this bit can be reset by writing a 1 to it. rbs2 port 2 ring beacon state change irq . when a ring beacon is received through port 2 and a change of state field in frame is detected when compared t o the previous beacon, this bit is set. when the rbm2 bit in the switch mask register is also set, an interrupt is delivered to the host cpu. this bit can be reset by writing a 1 to it. brx1 port 1 beacon received irq . when a ring beacon is received th rough port 1, this bit is set. when the brm1 bit in the switch mask register is also set, an interrupt is delivered to the host cpu. this bit can be reset by writing a 1 to it. brx2 port 2 beacon received irq . when a ring beacon is received through por t 2, this bit is set. when the brm2 bit in the switch mask register is also set, an interrupt is delivered to the host cpu. this bit can be reset by writing a 1 to it. bto1 port 1 beacon timeout irq . when a ring beacon is not received through port 1 wi thin the beacon timeout period, this bit is set. when the btm1 bit in the switch mask register is also set, an interrupt is delivered to the host cpu. this bit can be reset by writing a 1 to it. bto2 port 2 beacon timeout irq . when a ring beacon is not received through port 2 within the beacon timeout period, this bit is set. when the btm2 bit in the switch mask register is also set, an interrupt is delivered to the host cpu. this bit can be reset by writing a 1 to it. p1l port 1 loop irq . when a f rame with the same source address field as the host cpu mac address is received on port 1, this bit is set. when the p1lm bit in the switch control register is also set, an interrupt is delivered to the host cpu. this bit indicates a network misconnection resulting in a loop when not in ring redundancy mode. this should be flagged to the user, indicating a network fault condition. this bit can be cleared by writing a 1 to it.
FIDO2100 3 - port industrial ethernet dlr switch with ieee1588 data sheet april 10, 2013 64 support@innovasic.com document #: ia211111101 - 0 4 1 - 505 - 883 - 5263 uncontrolled when pr inted or copied 1 - 888 - 824 - 4184 p2l port 2 loop irq . when a frame with the same source address field as the h ost cpu mac address is received on port 2, this bit is set. when the p2lm bit in the switch control register is also set, an interrupt is delivered to the host cpu. this bit indicates a network misconnection resulting in a loop when not in ring redundancy mode. this should be flagged to the user, indicating a network fault condition. this bit can be cleared by writing a 1 to it. pit periodic interval timer irq . when the periodic interval timer expires (i.e. counts down to zero) this bit is set. when th e pitm bit in the switch mask register is also set, an interrupt is delivered to the host cpu. this bit can be reset by writing a 1 to it. lst1 port 1 link status . this bit reflects the port 1 link status from the p1_lnksts input signal. a 1 indicate s a valid link has been established (i.e. link pass status) and a 0 indicates link fail status. this is a read only bit, writes will be ignored. lst2 port 2 link status . this bit reflects the port 2 link status from the p2_lnksts input signal. a 1 ind icates a valid link has been established (i.e. link pass status) and a 0 indicates link fail status. this is a read only bit, writes will be ignored. 9 . 2.17 switch irq mask register mnemonic type offset bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 sw_mask r/w 0 x 54 pitm p 2 lm p 1 lm btm 2 btm 1 brm 2 brm 1 rbm 2 rbm 1 l 2 m l 1 m power - up defaults 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 l1m port 1 link status change irq mask . when this bit is set and the lirq1 bit in the switch event register is also set, then an interrupt is delivered to the host cpu. l2m port 2 link status change irq mask . when this bit is set and the lirq2 bit in the switch event register is also set, then an interrupt is delivered to the host cpu. rb m1 port 1 ring beacon state change irq mask . when this bit is set and the rbs1 bit in the switch event register is also set, an interrupt is delivered to the host cpu.
FIDO2100 3 - port industrial ethernet dlr switch with ieee1588 data sheet april 10, 2013 65 support@innovasic.com document #: ia211111101 - 0 4 1 - 505 - 883 - 5263 uncontrolled when pr inted or copied 1 - 888 - 824 - 4184 rbm2 port 2 ring beacon state change irq mask . when this bit is set and the rbs2 bit in the switch event register is also set, an interrupt is delivered to the host cpu. brm1 port 1 beacon received irq mask . when this bit is set and the brx1 bit in the switch event register is also set, an interrupt is delivered to the host cpu. brm2 p ort 2 beacon received irq mask . when this bit is set and the brx2 bit in the switch event register is also set, an interrupt is delivered to the host cpu. btm1 port 1 beacon timeout irq mask . when this bit is set and the bto1 bit in the switch event reg ister is also set, an interrupt is delivered to the host cpu. btm2 port 2 beacon timeout irq mask . when this bit is set and the bto2 bit in the switch event register is also set, an interrupt is delivered to the host cpu. p1lm port 1 loop irq mask . when this bit is set and the p1l bit in the switch event register is also set, an interrupt is delivered to the host cpu. p2lm port 2 loop irq mask . when this bit is set and the p2l bit in the switch event register is also set, an interrupt is delivered to the host cpu. pitm periodic interval timer irq mask . when this bit is set and the pit bit in the switch event register is also set, an interrupt is delivered to the host cpu. 9 . 2.18 port 1 seed register mnemonic type offset bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 prt 1 seed r/w 0 x 56 p 1 seed power - up defaults 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 p1seed port 1 seed . when the port 1 is in half duplex mode, this field can be used to load a 10 - bit seed value int o the linear feedback shift register that is used for the truncated binary exponential back off algorithm. 9 . 2.19 port 2 seed register mnemonic type offset bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 prt 2 seed r/w 0x 58 p 2 seed power - up defaults 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
FIDO2100 3 - port industrial ethernet dlr switch with ieee1588 data sheet april 10, 2013 66 support@innovasic.com document #: ia211111101 - 0 4 1 - 505 - 883 - 5263 uncontrolled when pr inted or copied 1 - 888 - 824 - 4184 p2seed port 2 seed . when the port 2 is in half duplex mode, this field can be used to load a 10 - bit seed value into the linear feedback shift register that is used for the truncated bin ary exponential back off algorithm. 9 . 2.20 host cpu mac address register mnemonic type offset bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 mac_lo_lo r/w 0 x 5 a macaddress [ 15:0 ] power - up defaults 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 mnemonic type offset bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 mac_lo_hi r/w 0 x 5 c macaddress [ 31:16 ] power - up defaults 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 mnemonic type offset bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 mac_hi_lo r/w 0 x 5 e macaddress [ 47:32 ] power - up defaults 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 the host cpu mac address register consists of three 16 - bit registers. this register should be set to the same unicast mac address as the host cpu mac address. for example to load the mac address 00 - 11 - 22 - 33 - 44 - 55, 0x0011 should be written to the mac_hi_lo, 0x2233 should be written to the mac_lo_hi, and 0x4455 should be written to the mac_lo_lo. the content of this register is used to perform filtering inside the switch. unica st frames cannot be received on the host until this register is set. the switch performs limited filtering of unicast frames. when a unicast frame is received on any port with a destination address equal to the host mac address, then that frame is delivere d to the host and is not forwarded to the other port. if a unicast frame is received on any port with a destination address not equal to the host mac address, then it is only forwarded to the other port, but not to the host. reads and writes of the three 1 6 - bit registers can be performed in any order.
FIDO2100 3 - port industrial ethernet dlr switch with ieee1588 data sheet april 10, 2013 67 support@innovasic.com document #: ia211111101 - 0 4 1 - 505 - 883 - 5263 uncontrolled when pr inted or copied 1 - 888 - 824 - 4184 9 . 2.21 multicast hash filter index and value registers mnemonic type offset bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 mchfi r/w 0 x 60 multicasthashindex[ 6:0 ] power - up defaults 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 mnemonic type offset bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 mchfv r/w 0 x 62 multicasthashvalue [ 15:0 ] power - up defaults 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 the multic ast hash filter consists of one hundred and twenty eight (128) 16 - bit registers. these 128 registers comprise a 2048 bin hash filter table, with bit 0 of register 0 corresponding to bin 0, and bit 15 of register 127 corresponding to bin 2047. in order to a ccess a filter register, the register number should first be written to the multicast hash filter index register. the register value can then be read from/written to through the multicast hash filter value register. when a multicast frame is received on an external port, the crc is computed on the received multicast address, and the bottom 11 bits of the crc are used to select the bin in the multicast hash filter table. if the selected bin is set, then the frame will be delivered to the host cpu. the algori thm used to compute the crc is the same as the ethernet crc. one version of the crc code is enclosed for reference. a table driven version of the ethernet crc code can also be used for speed. for example, to receive multicast address 01 - 00 - 5e - 00 - 01 - 81 (crc =0xd2e88860), register 6, bit 0 must be set. note that the filter table need not be set for receiving multicast ring frames.
FIDO2100 3 - port industrial ethernet dlr switch with ieee1588 data sheet april 10, 2013 68 support@innovasic.com document #: ia211111101 - 0 4 1 - 505 - 883 - 5263 uncontrolled when pr inted or copied 1 - 888 - 824 - 4184 // --------------------------------------------------------------------- const unsigned poly = 0xedb88320; // bit reverse of 0x 04c11db7 // --------------------------------------------------------------------- unsigned computecrc32 ( unsigned char *buf, int len) { unsigned crc = 0xffffffff; while ( -- len >= 0) { unsigned char data = *buf++; for ( int i = 0; i < 8; i++) { if ((crc ^ data) & 1) { crc >>= 1; crc ^= poly; } else crc >>= 1; data >>= 1; } } return (crc ^ 0xffffffff); } // --------------------------------------------------------------------- unsigned getmchash bin ( unsigned char mcadrs[6]) { unsigned crc = computecrc32 (( unsigned char *)mcadrs, 6); return (crc & 0x7ff); } // --------------------------------------------------------------------- 9 . 2.22 fre e running timer register mnemonic type offset bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 freetmr_lo r 0 x 64 freetimer [ 15:0 ] power - up defaults 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 mnemonic type offset bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 freetmr_hi r 0 x 66 freetimer [ 31:16 ] power - up defaults 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 the free running timer register consists of two 16 - bit registers. it is a 32 - bit free running up counter that counts at 100mhz and is used for transparent clock timestamps, delay measurements, and redundancy timestamps. it can be used to compare how recent a
FIDO2100 3 - port industrial ethernet dlr switch with ieee1588 data sheet april 10, 2013 69 support@innovasic.com document #: ia211111101 - 0 4 1 - 505 - 883 - 5263 uncontrolled when pr inted or copied 1 - 888 - 824 - 4184 timestamp is using 32 - bit unsigned arithmetic. at 100mhz the counter will reach the same value from the starting point in about 42 seconds, and so comparisons are not valid bey ond that. when performing reads, freetmr_lo should be read first, which will cause the higher 16 bits of the internal free timer register to be latched. when freetmr_hi is read later, the latched value will be returned. 9 . 2.23 periodic interval timer register mnemonic type offset bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 pittmo_lo r/w 0 x 68 pittimeout [ 15:0 ] power - up defaults 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 mnemonic type offset bits 15 14 13 12 11 1 0 9 8 7 6 5 4 3 2 1 0 pittmo_hi r/w 0 x 6 a pittimeout [ 31:16 ] power - up defaults 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 the periodic interval timer register consists of two 16 - bit registers. it is a 32 - bit down counter that counts at 50mhz. when the pit timer is enabled through the pite bit in the redundancy control register, the value from this register is loaded into the timer and countdown begins. when the timer reaches zero the pit bit in the switch event register is set, and the timer is loaded with value fr om this register again for the next count down. to prevent spurious interrupts, this register should be changed only when the pite bit is reset in the redundancy control register. the periodic interval timer can be used to provide an interrupt to generate ring beacons. 9 . 2.24 redundancy control register mnemonic type offset bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rdndnc_control r/w 0 x 6 c raf drm cns pite p 2 bte p 1 bte p 2 br p 1 br p 2 tb p 2 rb p 1 tb p 1 rb rspr dlr e resv power - up defaults 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 resv reserved , must be reset (0) dlre device level ring protocol enable . when this bit is set, FIDO2100 will support dlr protocol redundancy. if it is reset, FIDO2100 will not support ring redun dancy.
FIDO2100 3 - port industrial ethernet dlr switch with ieee1588 data sheet april 10, 2013 70 support@innovasic.com document #: ia211111101 - 0 4 1 - 505 - 883 - 5263 uncontrolled when pr inted or copied 1 - 888 - 824 - 4184 rspr ring supervisor enable . when this bit is set, FIDO2100 will support ring protocol redundancy as a ring supervisor. if it is reset, FIDO2100 will support ring protocol redundancy as a nonsupervisory device. depending on the setting of this bit, some logic will be enabled, some disabled and some function differently. details are described under appropriate sections. p1rb port 1 receive blocked . when this bit is set all frames received on port 1 will be dropped with the exception of following spe cial frames. ring beacon frames will be forwarded to host cpu if p1br bit is set. ring beacon frames with source mac address different from ring supervisor mac id register will always be forwarded to host cpu. ring neighbor check/sign on (multicast) frame s will be forwarded to host cpu. ring link/neighbor status frames or beacon failure notify frames with destination mac address same as host cpu mac address will be forwarded to host cpu. ring beacon frames will be forwarded to port 2 if rspr bit is not se t. p1tb port 1 transmit blocked . when this bit is set no frames will be transmitted on port 1 with the exception of following special frames. ring beacon frames from host cpu will be transmitted if rspr bit is set ( i.e. ring beacon will be transmitted on both ports). ring neighbor check/sign on (multicast) frames from host cpu will be transmitted if source port in frame matches port 1. ring beacon frames from port 2 will be transmitted if rspr bit is not set. p2rb port 2 receive blocked . when this bit i s set all frames received on port 2 will be dropped with the exception of following special frames. ring beacon frames will be forwarded to host cpu if p2br bit is set. ring beacon frames with source mac address different from ring supervisor mac id regis ter will always be forwarded to host cpu. ring neighbor check/sign on (multicast) frames will be forwarded to host cpu. ring link/neighbor status frames or beacon failure notify frames with destination mac address same as host cpu mac address will be forwa rded to host cpu. ring beacon frames will be forwarded to port 1 if rspr bit is not set. p2tb port 2 transmit blocked . when this bit is set no frames will be transmitted on port 2 with the exception of following special frames. ring beacon frames from ho st cpu will be transmitted if rspr bit is set ( i.e. ring beacon will be transmitted on both ports). ring neighbor check/sign on (multicast) frames from host cpu will be transmitted if source port in frame matches port 2. ring beacon frames from port 1 wil l be transmitted if rspr bit is not set. p1br port 1 beacon receive . when this bit is set, ring beacon frames received on port 1 will be forwarded to host cpu. if this bit is reset, ring beacons received
FIDO2100 3 - port industrial ethernet dlr switch with ieee1588 data sheet april 10, 2013 71 support@innovasic.com document #: ia211111101 - 0 4 1 - 505 - 883 - 5263 uncontrolled when pr inted or copied 1 - 888 - 824 - 4184 on port 1 will be dropped with following exception . ring beacon frames with source mac address different from ring supervisor mac id register will always be forwarded to host cpu. p2br port 2 beacon receive . when this bit is set, ring beacon frames received on port 2 will be forwarded to host cpu. if thi s bit is reset, ring beacons received on port 2 will be dropped with following exception. ring beacon frames with source mac address different from ring supervisor mac id register will always be forwarded to host cpu. p1bte port 1 beacon timeout enable . w hen this bit is set, port 1 beacon timeout timer is enabled. see beacon timeout register for details. p2bte port 2 beacon timeout enable . when this bit is set, port 2 beacon timeout timer is enabled. see beacon timeout register for details. pite periodic interval timer enable . when this bit is set, periodic interval timer is enabled. see periodic interval timer register for details. cns clear neighbor check request/sign on and link/neighbor status receive source id registers . when this bit is set, neighb or check request/sign on and link/neighbor status receive source id registers for both port 1 and port 2 will be cleared. this bit is self - clearing . drm drop reserved mac addresses . when this bit is set, ieee 802.1d reserved mac address 01 - 80 - c2 - 00 - 00 - 00 and cisco pvst+ mac address 01 - 00 - 0c - cc - cc - cd will not be forwarded from any port to other ports. raf receive announce frames . when this bit is set, ring announce frames will be forwarded to host cpu. 9 . 2.2 5 ring beacon state register mnemonic type offset bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rng_bcnstate r 0 x 6 e ringbeaconstate 2 [ 7:0 ] ringbeaconstate 1 [ 7:0 ] power - up defaults 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 the ring beacon state register contains the state flags field captured from the last beacon frame with the ring supervisor mac id register source address through ports 1 and 2. ringbeaconstate1 contains the state field captured from the last beacon frame through port 1 and ringbeaconstate2 contain s the state field captured from the last
FIDO2100 3 - port industrial ethernet dlr switch with ieee1588 data sheet april 10, 2013 72 support@innovasic.com document #: ia211111101 - 0 4 1 - 505 - 883 - 5263 uncontrolled when pr inted or copied 1 - 888 - 824 - 4184 beacon frame through port 2. a change of state in ringbeaconstate1 causes the rbs1 irq in the switch event register and a change of state in ringbeaconstate2 causes the rbs2 irq in the switch event register. 9 . 2.26 beacon timeout register mnemonic type offset bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bcntmo_lo r/w 0 x 70 beacon timeout [ 15:0 ] power - up defaults 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 mnemonic type offset bit s 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bcntmo_hi r/w 0 x 72 beacontimeout [ 31:16 ] power - up defaults 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 the beacon timeout register consists of two 16 - bit registers. the timeout value is used by both the port 1 beacon timeout timer and the port 2 beacon timeout timer. the beacon timeout timers are 32 - bit down counters that count at 50mhz. when the port 1 (or port 2) beacon timeout timer is enabled through the p1bte ( or p2bte) bit in the redundancy control register, the value from this register is loaded into respective timer and countdown begins. when a ring beacon is received on port 1 (or port 2) with the ring supervisor mac id register source address, without a crc error, the respective ports beacon timer is reloaded with the beacon timeout value and the countdown is started again. if the timer reaches zero the bto1 (or bto2) bit in the switch event register is set and the timer is loaded with the value from this register again for next count down. to prevent spurious int errupts, this register should be changed only when the p1bte and p2bte bits are reset in the redundancy control register. 9 . 2.27 port 1 beacon receive timestamp register mnemonic type offset b its 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 p 1 bcnts_lo r 0 x 74 beacontimestamp1 [ 15:0 ] power - up defaults 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 mnemonic type offset bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 p 1 bcnts_hi r 0 x 76 beacontimestamp1 [ 31:16 ] power - up defaults 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
FIDO2100 3 - port industrial ethernet dlr switch with ieee1588 data sheet april 10, 2013 73 support@innovasic.com document #: ia211111101 - 0 4 1 - 505 - 883 - 5263 uncontrolled when pr inted or copied 1 - 888 - 824 - 4184 the port 1 beacon receive timestamp register is comprised of two 16 - bit registers. it contains a snapshot of the free running timer when last ring beacon was received on port 1 with the ring supervisor mac id re gister source address. the two registers may be read in any order. however, since the registers may be updated between two reads when a new beacon is received, care should be taken to read the registers multiple times and only consider it as valid when two successive reads produce the same result. 9 . 2.28 port 2 beacon receive timestamp register mnemonic type offset bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 p 2 bcnts_lo r 0 x 78 beacon timestamp2 [15 : 0 ] power - up defaults 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 mnemonic type offset bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 p 2 bcnts_hi r 0 x 7 a beacontimestamp2 [ 31:16 ] power - up defaults 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 the port 2 beacon receive timestamp r egister is comprised of two 16 - bit registers. it contains a snapshot of the free running timer when the last ring beacon was received on port 2 with the ring supervisor mac id register source address. the two registers may be read in any order. however, s ince the registers may be updated between two reads when a new beacon is received, care should be taken to read the registers multiple times and only consider it as valid when two successive reads produce the same result. 9 . 2.29 port 1 neighbor check request/sign on receive source id register mnemonic type offset bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 p 1 nchksid_lo_lo r 0 x 7 c port1_neighbor_check_req_recv_srcid [ 15:0 ] power - up defaults 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 mnemonic type offset bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 p 1 nchksid_lo_hi r 0 x 7 e port1_neighbor_check_req_recv_srcid [ 31:16 ] power - up defaults 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 mnemonic type off set bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 p 1 nchksid_hi_lo r 0 x 80 port1_neighbor_check_req_recv_srcid [ 47:32 ] power - up defaults 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
FIDO2100 3 - port industrial ethernet dlr switch with ieee1588 data sheet april 10, 2013 74 support@innovasic.com document #: ia211111101 - 0 4 1 - 505 - 883 - 5263 uncontrolled when pr inted or copied 1 - 888 - 824 - 4184 the port 1 neighbor check request/sign on receive source id register is comprised of thr ee 16 - bit registers. it contains the source mac address of last neighbor check request/sign on (multicast) frame that was received on port 1. reads may be performed in any order. 9 . 2.30 port 2 neighbor check request/sign on receive source id register mnemonic type offset bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 p 2 nchksid_lo_lo r 0 x 82 port2_neighbor_check_req_recv_srcid [ 15:0 ] power - up defaults 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 mnemonic type offset bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 p 2 nchksid_lo_hi r 0 x 84 port2_neighbor_check_req_recv_srcid [ 31:16 ] power - up defaults 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 mnemonic type offset bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 p 2 nchksid_hi_lo r 0 x 86 port2_neighbor_check_req_recv_srcid [ 47:32 ] power - up defaults 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 the port 2 neighbor check request/sign on receive source id register is comprised of three 16 - bit registers. it contains the sour ce mac address of last neighbor check request/sign on (multicast) frame that was received on port 2. reads may be performed in any order. 9 . 2.31 port 1 link/neighbor status receive source id register mnemonic type offset bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 p 1 nstssid_lo_lo r 0 x 88 port1_neighbor_status_recv_srcid [ 15:0 ] power - up defaults 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 mnemonic type offset bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 p 1 nstssid_lo_hi r 0 x 8 a port1_neighbor_status_recv_srcid [ 31:16 ] power - up defaults 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 mnemonic type offset bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 p 1 nstssid_hi_lo r 0 x 8 c port1_neighbor_status_recv_srcid [47:32 ] power - up defaults 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
FIDO2100 3 - port industrial ethernet dlr switch with ieee1588 data sheet april 10, 2013 75 support@innovasic.com document #: ia211111101 - 0 4 1 - 505 - 883 - 5263 uncontrolled when pr inted or copied 1 - 888 - 824 - 4184 the port 1 link/neighbor status receive source id register is comprised of three 16 - bit registers. it contains the source mac address of the last link/neighbor status frame that was received on port 1 . reads may be performed in any order. 9 . 2.32 port 2 link/neighbor status receive source id register mnemonic type offset bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 p2nstssid_lo_l o r 0 x 8 e port2_neighbor_status_recv_srcid [ 15:0 ] power - up defaults 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 mnemonic type offset bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 p 2 nstssid_lo_hi r 0 x 90 port2_neighbor_status_recv_srcid [ 31:16 ] power - up defaults 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 mnemonic type offset bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 p 2 nstssid_hi_lo r 0 x 92 port2_neighbor_status_recv_srcid [ 47:32 ] power - up defaults 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 the port 2 link/neighbor status receive sour ce id register is comprised of three 16 - bit registers. it contains the source mac address of the last link/neighbor status frame that was received on port 2. reads may be performed in any order. 9 . 2.33 ring supervisor mac id register mnemonic type offset bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rngsprvsrid_lo_lo r 0 x 94 ring_supervisor_macid [ 15:0 ] power - up defaults 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 mnemonic type offset bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rngsprvsrid_lo_hi r 0 x 96 ring_supervisor_macid [ 31:16 ] power - up defaults 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 mnemonic type offset bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rngsprvsrid_hi_lo r 0 x 98 ring_supervisor_macid [ 47:32 ] power - up def aults 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
FIDO2100 3 - port industrial ethernet dlr switch with ieee1588 data sheet april 10, 2013 76 support@innovasic.com document #: ia211111101 - 0 4 1 - 505 - 883 - 5263 uncontrolled when pr inted or copied 1 - 888 - 824 - 4184 the ring supervisor mac id register is comprised of three 16 - bit registers. it contains the source mac address of active ring supervisor. this register must be set to the proper value in both ring supervisor and non - supervisor modes of operation, for the ring logic to function correctly. for example to load mac address 00 - 11 - 22 - 33 - 44 - 55, 0x0011 should be written to rngsprvsrid_hi_lo, 0x2233 should be written to rngsprvsrid _lo_hi, and 0x4455 should be written to rngs prvsrid _lo_lo. reads and writes may be performed in any order. 9 . 2.34 interface and media counters registers mnemonic type offset bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 p 1 rxgrpfrmcnt r 0 x 9 c port1_group_frame_recv_count [ 15:0 ] power - up defaults 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 mnemonic type offset bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 p 2 rxgrpfrmcnt r 0 x 9 e port2_group_frame_recv_count [ 15:0 ] power - up defaults 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 mnemonic type offset bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 p 1 rxunifrmcnt r 0 xa 0 port 1 _unicast_frame_recv_count[ 15:0 ] power - up defaults 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 mnemonic type offset bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 p2rx unifrmcnt r 0 xa 2 port 1 _unicast_frame_recv_count[ 15:0 ] power - up defaults 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 mnemonic type offset bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 p 1 rxbytcnt_lo r 0 xa 4 port 1 _recv_byte_count[ 15:0 ] power - up defaults 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 mnemonic type offset bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 p 1 rxbytcnt_hi r 0 xa 6 port 1 _recv_byte_count[ 31:16 ] power - up defaults 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 mnemonic type offset bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 p 2 rxbytcnt_lo r 0 xa 8 port 2 _recv_byte_count[ 15:0 ] power - up defaults 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
FIDO2100 3 - port industrial ethernet dlr switch with ieee1588 data sheet april 10, 2013 77 support@innovasic.com document #: ia211111101 - 0 4 1 - 505 - 883 - 5263 uncontrolled when pr inted or copied 1 - 888 - 824 - 4184 mnemonic type offset bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 p 2 rxbytcnt_hi r 0 xaa port 2 _recv_byte_count[ 31:16 ] power - up defaults 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 mnemonic type offset bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 p 1 rxlrgfrmcnt r 0 xac port 1 _large_error_frame_recv_count[ 15:0 ] power - up defaults 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 mnemonic type offset bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 p 2 rxlrgfrmcnt r 0 xae port 2 _large_error_frame_recv_count[ 15:0 ] power - up defaults 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 mnemonic type offset bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 p 1 rxalnfrmcnt r 0 xb 0 port1_align_error_frame_recv_count[15:0 ] power - up defaults 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 mnemonic type offset bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 p 2 rxalnfrmcnt r 0 xb 2 port 2 _align_error_frame_recv_count[ 15:0 ] power - up defaults 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 mnemonic type offs et bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 p 1 rxfcsfrmcnt r 0 xb 4 port 1 _fcs_error_frame_recv_count[ 15:0 ] power - up defaults 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 mnemonic type offset bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 p 2 rxfcsfrmcnt r 0 xb 6 port2_f cs_error_frame_recv_count[ 15:0 ] power - up defaults 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 mnemonic type offset bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 p 1 rxerrfrmcnt r 0 xb 8 port 1 _recv_error_frame_count[ 15:0 ] power - up defaults 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 mnemonic type offset bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 p 2 rxerrfrmcnt r 0 xba port 2 _recv_error_frame_count[ 15:0 ] power - up defaults 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
FIDO2100 3 - port industrial ethernet dlr switch with ieee1588 data sheet april 10, 2013 78 support@innovasic.com document #: ia211111101 - 0 4 1 - 505 - 883 - 5263 uncontrolled when pr inted or copied 1 - 888 - 824 - 4184 mnemonic type offset bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 p1txgr pfrmcnt r 0 xbc port 1 _group_frame_xmit_count[ 15:0 ] power - up defaults 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 mnemonic type offset bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 p 2 txgrpfrmcnt r 0 xbe port 2 _group_frame_xmit_count[ 15:0 ] power - up defaults 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 mnemonic type offset bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 p 1 txunifrmcnt r 0 xc 0 port 1 _unicast_frame_xmit_count[ 15:0 ] power - up defaults 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 mnemonic type offset bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 p 2 txunifrmcnt r 0 xc 2 port 2 _unicast_frame_xmit_count[ 15:0 ] power - up defaults 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 mnemonic type offset bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 p 1 txbytcnt_lo r 0 xc 4 port 1 _xmit_byte_count[ 15:0 ] power - up defaul ts 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 mnemonic type offset bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 p 1 txbytcnt_hi r 0 xc 6 port 1 _xmit_byte_count[ 31:16 ] power - up defaults 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 mnemonic type offset bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 p 2 txbytcnt_lo r 0 xc 8 port 2 _xmit_byte_count[ 15:0 ] power - up defaults 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 mnemonic type offset bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 p 2 txbytcnt_hi r 0 xca port 2 _xmit_byte_count[ 31:16 ] power - up defaults 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 mnemonic type offset bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 p 1 txsclfrmcnt r 0 xcc port 1 _xmit_single_collision_frame_count[ 15:0 ] power - up defaults 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
FIDO2100 3 - port industrial ethernet dlr switch with ieee1588 data sheet april 10, 2013 79 support@innovasic.com document #: ia211111101 - 0 4 1 - 505 - 883 - 5263 uncontrolled when pr inted or copied 1 - 888 - 824 - 4184 mnemonic type offset bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 p 2 txsclfrmcnt r 0 xce port 2 _xmit_single_collision_frame_count[ 15:0 ] power - up defaults 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 mnemonic type offset bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 p 1 txmclfrmcnt r 0 xd 0 port1_xmit_mu ltiple_collision_frame_count[ 15:0 ] power - up defaults 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 mnemonic type offset bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 p 2 txmclfrmcnt r 0 xd 2 port 2 _xmit_multiple_collision_frame_count[ 15:0 ] power - up defaults 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 mnemonic type offset bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 p 1 txxclfrmcnt r 0 xd 4 port 1 _xmit_excessive_collision_frame_count[ 15:0 ] power - up defaults 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 mnemonic type offset bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 p 2 txxclfrmcnt r 0 xd 6 port 2 _xmit_excessive_collision_frame_count[ 15:0 ] power - up defaults 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 mnemonic type offset bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 p 1 txerrfrmcnt r 0 xd 8 port1_xmit_error_frame_ count[ 15:0 ] power - up defaults 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 mnemonic type offset bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 p 2 txerrfrmcnt r 0 xda port 2 _xmit_error_frame_count[ 15:0 ] power - up defaults 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 the interface a nd media counters registers can be used to implement ethernet/ip link object. to avoid a rollover issue with these registers, the firmware should scan these registers at least once every 200 milliseconds or on demand, and calculate the increase in counters using unsigned 16 - bit arithmetic. the computed increase must be added to firmware maintained 32 - bit counters of the ethernet/ip link object. the counters can be reset by resetting the respective port. ? p1rxgrpfrmcnt : this 16 - bit counter reflects multicast and broadcast frames received without errors on port 1.
FIDO2100 3 - port industrial ethernet dlr switch with ieee1588 data sheet april 10, 2013 80 support@innovasic.com document #: ia211111101 - 0 4 1 - 505 - 883 - 5263 uncontrolled when pr inted or copied 1 - 888 - 824 - 4184 ? p2rxgrpfrmcnt : this 16 - bit counter reflects multicast and broadcast frames received without errors on port 2. ? p1rxunifrmcnt : this 16 - bit counter reflects unicast frames received without errors on por t 1. ? p2rxunifrmcnt : this 16 - bit counter reflects unicast frames received without errors on port 2. ? p1rxbytcnt : this 32 - bit counter reflects byte count of unicast, multicast and broadcast frames received without errors on port 1. since this register may be updated while the reads are under progress, this counter must be read twice. only when two successive reads produce same result should the value be used. ? p2rxbytcnt : this 32 - bit counter reflects byte count of unicast, multicast and broadcast frames receive d without errors on port 2. since this register may be updated while the reads are under progress, this counter must be read twice. only when two successive reads produce same result should the value be used. ? p1rxlrgfrmcnt : this 16 - bit counter reflects fra mes larger than 1522 bytes including crc received on port 1. such frames are not ieee 802.3 compliant. ? p2rxlrgfrmcnt : this 16 - bit counter reflects frames larger than 1522 bytes including crc received on port 2. such frames are not ieee 802.3 compliant. ? p1r xalnfrmcnt : this 16 - bit counter reflects frames with alignment error i.e. non - integral number of bytes received on port 1. ? p2rxalnfrmcnt : this 16 - bit counter reflects frames with alignment error i.e. non - integral number of bytes received on port 2. ? p1rxfcs frmcnt : this 16 - bit counter reflects frames with frame check sequence (crc) error received on port 1. ? p2rxfcsfrmcnt : this 16 - bit counter reflects frames with frame check sequence (crc) error received on port 2. ? p1rxerrfrmcnt : this 16 - bit counter reflects f rames with other errors including frames shorter than 64 bytes received on port 1. ? p2rxerrfrmcnt : this 16 - bit counter reflects frames with other errors including frames shorter than 64 bytes received on port 2.
FIDO2100 3 - port industrial ethernet dlr switch with ieee1588 data sheet april 10, 2013 81 support@innovasic.com document #: ia211111101 - 0 4 1 - 505 - 883 - 5263 uncontrolled when pr inted or copied 1 - 888 - 824 - 4184 ? p1txgrpfrmcnt : this 16 - bit counter reflects m ulticast and broadcast frames transmitted without errors on port 1. ? p2txgrpfrmcnt : this 16 - bit counter reflects multicast and broadcast frames transmitted without errors on port 2. ? p1txunifrmcnt : this 16 - bit counter reflects unicast frames transmitted with out errors on port 1. ? p2txunifrmcnt : this 16 - bit counter reflects unicast frames transmitted without errors on port 2. ? p1txbytcnt : this 32 - bit counter reflects byte count of unicast, multicast and broadcast frames transmitted without errors on port 1. sinc e this register may be updated while the reads are under progress, this counter must be read twice and only when two successive reads produce same result should the value be used. ? p2txbytcnt : this 32 bit counter reflects byte count of unicast, multicast an d broadcast frames transmitted without errors on port 2. since this register may be updated while the reads are under progress, this counter must be read twice and only when two successive reads produce same result should the value be used. ? p1txsclfrmcnt : this 16 - bit counter reflects frames transmitted after exactly one collision in half duplex mode on port 1. ? p2txsclfrmcnt : this 16 - bit counter reflects frames transmitted after exactly one collision in half duplex mode on port 2. ? p1txmclfrmcnt : this 16 - bit counter reflects frames transmitted after more than one collision in half duplex mode on port 1. ? p2txmclfrmcnt : this 16 - bit counter reflects frames transmitted after more than one collision in half duplex mode on port 2. ? p1txxclfrmcnt : this 16 - bit counter reflects frames dropped after excessive (16) collisions in half duplex mode on port 1. ? p2txxclfrmcnt : this 16 - bit counter reflects frames dropped after excessive (16) collisions in half duplex mode on port 2. ? p1txerrfrmcnt : this 16 - bit counter reflects fra mes truncated with error during transmission on port 1.
FIDO2100 3 - port industrial ethernet dlr switch with ieee1588 data sheet april 10, 2013 82 support@innovasic.com document #: ia211111101 - 0 4 1 - 505 - 883 - 5263 uncontrolled when pr inted or copied 1 - 888 - 824 - 4184 ? p2txerrfrmcnt : this 16 - bit counter reflects frames truncated with error during transmission on port 2. 9 . 2.35 beacon generation control register mnemonic type offset bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bcngencntrl r/w 0 xdc bgrst bge 2 bge 1 bite power - up defaults 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bite beacon interval timer enable . when this bit is set, beacon interval timer is enabled. its a periodic timer and when the interval expires, beacon generation is triggered if bge1/bge2 are set and the timer is restarted. in order to immediately trigger a beacon frame on ports, this bit should be reset and set. bge1 beacon generati on enable for port 1 . when this bit is set, dlr beacon frame generation is enabled on port 1. frame sequence id will be automatically generated. bge2 beacon generation enable for port 2 . when this bit is set, dlr beacon frame generation is enabled on port 2. frame sequence id will be automatically generated. bgrst beacon generation reset . when this bit is set, all beacon frame generation logic will be held in reset. 9 . 2.36 beacon interval register mnemonic typ e offset bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bcnintrvl_lo r /w 0 xde beaconinterval[ 15:0 ] power - up defaults 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 mnemonic type offset bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bcnintrvl_ hi r /w 0 xe 0 beaconinterval[31 : 16 ] power - up defaults 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 the beacon interval register consists of two 16 - bit registers. it is a 32 - bit counter that counts at 50mhz and is used to trigger beacon frame generation on port(s) when it is enabled and expires. s ee bite bit in beacon generation control register for more details.
FIDO2100 3 - port industrial ethernet dlr switch with ieee1588 data sheet april 10, 2013 83 support@innovasic.com document #: ia211111101 - 0 4 1 - 505 - 883 - 5263 uncontrolled when pr inted or copied 1 - 888 - 824 - 4184 9 . 2.37 beacon frame data index and value registers mnemonic type offset bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bcndata idx r/w 0 xe 2 beacondataindex[ 5:0 ] power - up defaults 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 mnemonic type offset bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bcndataval r/w 0 xe 4 beacondatavalue[ 7:0 ] power - up defaults 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 the beacon frame data index and value registers provide the means to define appropriate contents for the dlr beacon frame. for dlr beacon frames, bytes 0 to 39 must be defined. the sequence id for beacon frame will be automatically generated and will be inserted at correct position. note that byte index greater than or equal to 40 should not be defined. 9 . 2.38 FIDO2100 version register mnemonic type offset bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 embswtchver r 0 xe 6 majorversion[ 7:0 ] minorversion[ 7:0 ] power - up defaults 0 0 0 0 0 0 0 1 0 0 1 1 1 1 0 1 the FIDO2100 version register is a read only register that provides major and minor version information.
FIDO2100 3 - port industrial ethernet dlr switch with ieee1588 data sheet april 10, 2013 84 support@innovasic.com document #: ia211111101 - 0 4 1 - 505 - 883 - 5263 uncontrolled when pr inted or copied 1 - 888 - 824 - 4184 10 revision history table 16 document revision history date revision description page(s) september 10 , 2012 00 first edition released . na october 1, 2012 01 updated section 5.1 pll supply. 37 december 3, 2012 02 added thermal characteristics and power consumption inform ation. 37, 38 february 12, 2013 03 corrected cut - through times (changed ns to s) 19 april 10, 2013 04 clarified junction temperature parameter name 37 11 for additional information the innovasic support team is continually planning and creating tools for your use. visit http://www.innovasic.com for up - to - date documentation and software. our goal is to provide timely, complete, accurate, useful, and easy - to - understand information. please feel free to contact ou r experts at innovasic at any time with suggestions, comments, or questions. innovasic support team 5635 jefferson st. ne, suite a albuquerque, nm 87109 phone: +1 - 505 - 883 - 5263 fax: (505) 883 - 5477 toll free: (888) 824 - 4184 us e - mail: support@innovasic.com w ebsite: http://www.innovasic.com

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